Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Host Extend Register Status (HECI1_HERS) – Offset bc
This register is used to communicate the CSE FW measurement
status information to host.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31 | 0h | RO/V | Extend Register Valid (ERV) Set by FW after all FW has been |
30 | 1h | RO | Extend Feature Present (EFP) This bit is hardwired to 1 to allow |
29 | 0h | RO/V | Extend Complete (ERC) This bit is set by OCS hardware at the end of an |
28:20 | 0h | RO | Reserved (RSVD_28_20) Reserved. |
19:16 | 0h | RO/V | DFX Secure Bus Policy Value (DSP) Reflects the security bus policy value from the Design for anything Aggregator. |
15:4 | 0h | RO | Reserved (RSVD_15_4) Reserved. |
3:0 | 0h | RO/V | Extend Register Algorithm (ERA) This field indicates the hash |