Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Compute Tile Early Power-on Configuration (CPU_EPOC) – Offset 18ec
Compute Tile Early Power on Configuration
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:22 | 0h | RO | Reserved |
21:20 | 0h | RO/V | Crystal Frequency[2:1] (XTAL_FREQ_MSB) Along with XTAL_FREQ_LSB the 3 bit field reflects the frequency |
19 | 0h | RO/V | EPOC Data[19] (EPOC_DATA_19) DAM ( Delayed Authentication Mode |
18 | 0h | RO | Reserved |
17 | 0h | RO/V | Crystal Frequency [0] (XTAL_FREQ_LSB) See XTAL_FREQ_MSB |
16 | 0h | RO | Reserved |
15 | 0h | RO/V | EPOC Data[15] (EPOC_DATA_15) the values comes from DRV_CPU_EPOC from PMU space which is driven by PMC FW. |
14:8 | 0h | RO | Reserved |
7:3 | 0h | RW/L | EPOC Data [7:3] (EPOC_DATA_7_3) EPOC Data [7:3] |
2 | 0h | RO | Reserved |
1:0 | 0h | RW/L | EPOC Data [1:0] (EPOC_DATA_1_0) EPOC Data [1:0] |