Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Pad Configuration Lock (PADCFGLOCK_GPP_S_0) – Offset 110
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:8 | 0h | RO | Reserved (RSVD_0)
|
7 | 0h | RW | Pad Config Lock (PADCFGLOCK_xxgpp_s_7) Same description as bit 0 |
6 | 0h | RW | Pad Config Lock (PADCFGLOCK_xxgpp_s_6) Same description as bit 0 |
5 | 0h | RW | Pad Config Lock (PADCFGLOCK_xxgpp_s_5) Same description as bit 0 |
4 | 0h | RW | Pad Config Lock (PADCFGLOCK_xxgpp_s_4) Same description as bit 0 |
3 | 0h | RW | Pad Config Lock (PADCFGLOCK_xxgpp_s_3) Same description as bit 0 |
2 | 0h | RW | Pad Config Lock (PADCFGLOCK_xxgpp_s_2) Same description as bit 0 |
1 | 0h | RW | Pad Config Lock (PADCFGLOCK_xxgpp_s_1) Same description as bit 0 |
0 | 0h | RW | Pad Config Lock (PADCFGLOCK_xxgpp_s_0) Pad Configuration Lock locks specific register fields in the GPP specific registers from being configured. The registers affected become Read-Only and software writes to these registers have no effect. |