Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
REG IER (IER) – Offset 4
Interrupt Enable Register. IER mode is only available when LCR register [7] (DLAB bit) = 0.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:8 | 0h | RO | Reserved |
7 | 0h | RW | PTIME (PTIME) THRE Interrupt Mode Enable: This is used to enable/disable the generation of THRE |
6:4 | 0h | NA | Res_6_4 (Res_6_4) Reserved |
3 | 0h | RW | EDSSI (EDSSI) Enable Modem Status Interrupt: This is used to enable/disable the generation of |
2 | 0h | RW | ELSI (ELSI) Enable Receiver Line Status Interrupt. This is used to enable/disable the generation |
1 | 0h | RW | ETBEI (ETBEI) Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the |
0 | 0h | RW | ERBFI (ERBFI) Enable Received Data Available Interrupt. This is used to enable/disable the |