Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
REG SRBR_STHR1 (SRBR_STHR1) – Offset 34
Shadow Receive Buffer Register and Shadow Transmit Holding Register 1
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:8 | 0h | RO | Reserved |
7:0 | 0h | RW | srbr_sthr1 (srbr_sthr1) This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register |