Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Register D Flag Register (Register_D) – Offset d
RTC Index: 0Dh
Attribute: Read/Write
Default Value: 10UUUUUU
Size: 8-bit
Lockable: No Power
Well: RTC
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
7 | 1h | RO | Valid RAM and Time Bit (VRT) This bit is hard-wired to 1 in the RTC power well. This bit should always be written as a 0 for write cycle, however it will return a 1 for read cycles. |
6 | 0h | RO | Reserved (RSVD) This bit always returns a 0 and should be set to 0 for write cycles. |
5:0 | 0h | RW | Date Alarm (Date_Alarm) These bits store the date of month alarm value. If set to 000000, then a dont care state is assumed. The host must configure the dates alarm for these bits to do anything, yet they can be written at any time. If the date alarm is not enabled, these bits will return zeros to mimic the functionality of the Motorola 146818B. These bits are not affected by any reset assertion. |