Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Port VC Control (PVCC) – Offset 28c
This is the Port VC Control registers. Refer description for each individual field below for more details of the register functionality.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
15:4 | 0h | RO | Reserved (RSVD_M) Reserved. |
3:1 | 0h | RW | VC Arbitration Select (VCAS) Used by software to configure the VC arbitration by selecting one of the supported VC Arbitration schemes indicated by the VC Arbitration Capability field in the |
0 | 0h | WO | Load VC Arbitration Table (LVCAT) Used by software to update the VC Arbitration Table. This bit is valid when the selected VC |