Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Touch Device Interrupt Cause register Format Configuration Register 1 (THC_M_PRT_DEVINT_CFG_1) – Offset 10ec
Touch Device Interrupt Cause register Format Configuration
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:16 | 2h | RW/L | Value of Interrupt Type Touch Data (THC_M_PRT_INTTYP_DATA_VAL) This is a bit mask where SW can set one or multiple bits |
15 | 0h | RW | Enable bit to send Interrupt Cause Register (THC_M_PRT_SEND_ICR_US_EN) When this bit is 1 and INT_SW_DMA_EN=0, in RXDMA mode, THC will send the touch device Interrupt Cause Register value of the first uFrame in every frame as the first DW in the corresponding PRD table. |
14:10 | 1eh | RW/L | Bit Offset of End of Frame (THC_M_PRT_EOF_OFFSET) Touch device's 'End of Frame' field's starting bit position |
9:5 | 4h | RW/L | Length of Interrupt Type (THC_M_PRT_INTTYP_LEN) Touch device's 'interrupt Type' field's length in the |
4:0 | 0h | RW/L | Bit Offset of Interrupt Type (THC_M_PRT_INTTYP_OFFSET) Touch device's 'interrupt Type' fields starting bit position |