Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Power Management Data, Control/Status Register Bridge Support Extensions, Control And Status (KT_HOST_PMD_PMCSRBSE_PMCSR) – Offset 54
This register contains the power management data, control and status register bridge support extensions, control and status registers.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:24 | 0h | RO | Data (DATA) Not implemented. Hardwired to 0. |
23:16 | 0h | RO | Control/Status Register Bridge Support Extensions (CSRBSE) Not implemented. Hardwired to 0. |
15 | 0h | RO | PME Status (PMESTS) This bit is set when the function would normally assert the PME signal |
14:13 | 0h | RO | Data Scale (DS) Not implemented. Hardwired to 0. |
12:9 | 0h | RO | Data Select (DSEL) Not implemented. Hardwired to 0. |
8 | 0h | RO | PME Enable (PMEEN) A 1 enables the function to assert PME. When 0, PME assertion is disabled. |
7:4 | 0h | RO | Reserved (RSVD1)
|
3 | 1h | RO | No Soft Reset (NSR) When set to 1, this bit indicates that |
2 | 0h | RO | Reserved (RSVD0)
|
1:0 | 0h | RW | Power State (PWRST) This 2-bit field is used both to determine |