Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Power Control Enables (THC_CFG_PCE) – Offset a4
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:6 | 0h | RO | Reserved (RSVD_31_6) Reserved. |
5 | 0h | RW/V | Hardware Autonomous Enable (HAE) If set, then the PGCB may request a PG whenever it is idle. |
4 | 0h | RW | Reserved (RSVD_4) Reserved. |
3 | 1h | RW/V | Sleep Enable (SE) if clear, then IP will never asset Sleep to the retention flops. If set, then IP may assert Sleep during PG'ing. Note that some platforms may default this bit to 0, others to 1. |
2 | 0h | RW | D3-Hot Enable (D3HE) if set, then IP will power-gate when idle and the PMCSR[1:0] register in the IP = 11. |
1 | 0h | RW | I3 Enable (I3E) if set, then IP will power-gate when idle and the D0i3 register (D0i3C[2] = 1) is set. |
0 | 0h | RW | Software PowerGate Enable (SPE) If this bit is set, the IP will power-gate. |