Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
HSIO Power Management Configuration Reg 2 (MODPHY_PM_CFG2) – Offset 10c4
This register contains misc fields used to configure power management behavior with respect to HSIO.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:12 | 0h | RO | Reserved |
11:0 | fffh | RW | HSIO Lane Sx SUS Well Power Gating Policy [11:0] (MLSXSWPGP) This is a bit per lane that controls SUS Well Power Gating for a HSIO lane when system is in Sx. |