Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Power Scheduler Control-1 (PWR_SCHED_CTRL2) – Offset 8144
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:27 | 0h | RW | Reserved (RSVD0) Reserved |
26:24 | 0h | RO | Reserved |
23:21 | 0h | RW | Reserved (RSVD1) Reserved |
20:10 | 0h | RO | Reserved |
9 | 1h | RW | HS Interrupt-OUT Alarm (HS_INT_OUT_ALRM) HS Interrupt OUT Alarm |
8 | 0h | RW | HS Interrupt-IN Alarm (HS_INT_IN_ALRM) HS Interrupt IN Alarm (HSII): |
7 | 0h | RW | SS Interrupt-OUT FC Alarm (SS_INT_OUT_FC_ALRM) SS Interrupt OUT Alarm |
6 | 0h | RW | SS Interrupt-IN Alarm (SS_INT_IN_FC_ALRM) SS Interrupt IN Alarm |
5 | 1h | RW | SS Interrupt-OUT and not in FC Alarm (SS_INT_OUT_ALRM) SS Interrupt OUT and not in FC Frame Alarm |
4 | 1h | RW | SS Interrupt-IN and not in FC Alarm (SS_INT_IN_ALRM) SS Interrupt IN and not in FC Frame Alarm |
3 | 1h | RW | HS ISO-OUT Alarm (HS_ISO_OUT_ALRM) HS ISO-OUT Alarm |
2 | 1h | RW | HS ISO-IN Alarm (HS_ISO_IN_ALRM) HS ISO-IN Alarm |
1 | 1h | RW | SS ISO-OUT Alarm (SS_ISO_OUT_ALRM) SS ISO-OUT Alarm |
0 | 1h | RW | SS ISO-IN Alarm (SS_ISO_IN_ALRM) SS ISO-IN Alarm |