Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
RIRB Write Pointer (RIRBWP) – Offset 58
This register reports the write pointer of the Response Input Ring Buffer.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
15 | 0h | WO | RIRB Write Pointer Reset (RIRBWPRST) Software writes a 1 to this bit to reset the RIRB Write Pointer to 0s. The RIRB DMA engine must be stopped prior to resetting the Write Pointer or else DMA transfer may be corrupted. This bit will always be read as 0. |
14:8 | 0h | RO | Reserved |
7:0 | 0h | RO/V | RIRB Write Pointer (RIRBWP) Indicates the last valid RIRB entry written by the DMA controller. Software reads this field to determine how many responses it can read from the RIRB. The value read indicates the RIRB Write Pointer offset in 2 Dword RIRB entry units (since each RIRB entry is 2 Dwords long). Supports up to 256 RIRB entries (256 x 8B=2KB). This field may be read while the DMA engine is running. |