Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
BIOS Assigned Thermal Base Address (TBARB) – Offset 40
This BAR creates 4K bytes of memory space to signify the base address of Thermal memory mapped configuration registers. This memory space is active when TBARB.SPTYPEN is asserted. This BAR is owned by the BIOS, and allows the BIOS to locate the Thermal registers in system memory space. It is up to the SW to manage having 2 independent code routines both accessing a single hardware resource (the TS).
NOTE: This register has its own enable, bit [0] below. TBARB and TBARBH decode must NOT be affected by MSE or D3 condition. BIOS and/or SMM use this register outside of official OS visibility. Therefore this BAR must not be affected by OS setting or clearing of MSE or the power state.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:12 | 00000h | RW | Thermal Base Address (TBA) Base address for the Thermal logic memory mapped configuration registers. 4KB bytes are requested by hardwiring bits 11:4 to 0's. |
11:4 | - | - | Reserved
|
3 | 0b | RO | Prefetchable (PREF) Indicates that this BAR is NOT pre-fetchable. |
2:1 | 10b | RO | Address Range (ADDRNG) Indicates that this BAR can be located anywhere in 64 bit address space. |
0 | 0b | RW | Space Type Enable (SPTYPEN) When set to 1b by software, enables the decode of this memory BAR. |