Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
Link Error for Slave 0 (LNKERR_SLV0) – Offset 4050
This register is used to control link error reporting for the eSPI Slave 0.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31 | 0b | RW/1C/V | eSPI Link and Slave Channel Recovery Required (SLCRR) HW sets this bit when it has detected a Type 1 Fatal Error condition, for any channel (LFET1C is non-zero). Setting of this bit will trigger an error handling sequence by the eSPI-MC, followed by the suspension of all HW initiated transactions on the eSPI link with the Slave. SW must clear this bit (by writing a 1 to it) after it has taken all necessary actions to recover the link. This indicates the eSPI-MC to resume HW initiated transactions with the Slave. |
30:23 | - | - | Reserved
|
22:21 | 0b | RW | Fatal Error Type 1 Reporting Enable (LFET1E) 00: Disable Fatal Error Type 1 Reporting |
20 | 0b | RW/1C/V | Fatal Error Type 1 Reporting Status (LFET1S) This field is set by hardware if a Link Fatal Error Type 1 condition is detected on the eSPI link (any transaction). Software must clear this bit by writing a 1 to it. |
19:16 | 0h | RO/V | Link Fatal Type 1 cause (LFET1C) 4'h0: No error |
15:8 | FFh | RO/V | Link Fatal Error Type 1 Cycle Type (LFET1CTYP) When LFET1C is set, this field reflects the Cycle Type for the transaction that encountered the Fatal Error Type 1. If no valid Cycle Type exists w.r.t. the Command (LFET1CMD), this field is set to 8hFF to indicate that it should be ignored. |
7:0 | 0h | RO/V | Link Fatal Error Type 1 Command (LFET1CMD) When LFET1C is set, this field reflects the Command for the transaction that encountered the Fatal Error Type 1. |