Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
Destination Scatter (DSR0) – Offset 850
NOTE: DSR0 is for DMA Channel 0. The same register definition, DSR1, is available for Channel 1 at address 8A8h.
DSR0(CH0): offset 850h
DSR1(CH1): offset 8A8h
The Destination Scatter register contains two fields: Destination scatter count field (DSRx.DSC) . Specifies the number of contiguous destination transfers of CTLx.DST_TR_WIDTH between successive scatter boundaries. Destination scatter interval field (DSRx.DSI) . Specifies the destination address increment/decrement in multiples of CTLx.DST_TR_WIDTH on a scatter boundary when scatter mode is enabled for the destination transfer. The CTLx.DINC field controls whether the address increments or decrements. When the CTLx.DINC field indicates a fixed address control, then the address remains constant throughout the transfer and the DSRx register is ignored.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:20 | 0h | RW | Destination Scatter Count (DSC)
|
19:0 | 0h | RW | Destination Scatter Interval (DSI)
|