Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
Normal Interrupt Signal Enable (normalintrsigena) – Offset 38
This register is used to enable the Normal Interrupt Signal register. All the bits are RW, except for Reserved bits, and defined as follows:
0 - Masked
1 - Enabled.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
14 | 0h | RW | Boot Terminate Interrupt Signal Enable (bootintr_sigena)
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13 | 0h | RW | Boot ack rcv Signal Enable (bootack_rcvsigena)
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12 | 0h | RW | Re-Tuning Event Signal Enable (retune_eventsigena)
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11 | 0h | RW | INT_C Signal Enable (int_c_sigena)
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10 | 0h | RW | INT_B Signal Enable (int_b_sigena)
|
9 | 0h | RW | INT_A Signal Enable (int_a_sigena)
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8 | 0h | RW | Card Interrupt Signal Enable (sdhcregset_cardintstsena)
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7 | 0h | RW | Card Removal Signal Enable (sdhcregset_cardremstsena)
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6 | 0h | RW | Card Insertion Signal Enable (sdhcregset_cardinsstsena)
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5 | 0h | RW | Buffer Read Ready Signal Enable (buffrd_readtsigena)
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4 | 0h | RW | Buffer Write Ready Signal Enable (buffwr_readtsigena)
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3 | 0h | RW | DMA Interrupt Signal Enable (dmaintrsigena)
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2 | 0h | RW | Block Gap Event Signal Enable (blockgap_eventsigena)
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1 | 0h | RW | Transfer Complete Signal Enable (xfrcmpltsigena)
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0 | 0h | RW | Command Complete Signal Enable (cmdcmpltsigena)
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