Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
Pad Configuration DW0 (PAD_CFG_DW0_vGPIO_39) – Offset d00
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:30 | 01b | RO | Pad Reset Config (PADRSTCFG) This register controls which reset is used to resetGPIO pad register fields in PAD_CFG_DW0 and PAD_CFG_DW1 registers. This bit ishardwired to 01. |
29:24 | - | - | Reserved
|
23 | 0b | RW | RX Invert (RXINV) This bit determines if the selected pad state should go through the polarity inversion stage. This field only makes sense when the RX buffer is configured as an input in either GPIO Mode or native function mode. The polarity inversion takes place at the mux node of raw vs filtered or non-filtered RX pad state, as determined by |
22:21 | - | - | Reserved
|
20 | 0b | RO | GPIO Input Route IOxAPIC (GPIROUTIOXAPIC) Determine if the pad can be routed to cause peripheral IRQ when configured in GPIO input mode. If the pad is not configured in GPIO input mode, this field has no effect. 0 = Routing does not cause peripheral IRQ |
19 | 0b | RO | GPIO Input Route SCI (GPIROUTSCI) Determine if the pad can be routed to cause SCI when configured in GPIO input mode. If the pad is not configured in GPIO input mode, this field has no effect. 0 = Routing does not cause SCI |
18 | 0b | RO | GPIO Input Route SMI (GPIROUTSMI) Determine if the pad can be routed to cause SMI when configured in GPIO input mode. If the pad is not configured in GPIO input mode, this field has no effect. 0 = Routing does not cause SMI. |
17 | 0b | RO | GPIO Input Route NMI (GPIROUTNMI) Determine if the pad can be routed to cause NMI when configured in GPIO input mode. If the pad is not configured in GPIO input mode, this field has no effect. 0 = Routing does not cause NMI. |
16:11 | - | - | Reserved
|
10 | 1b | RW | Pad Mode (PMODE) This field determines whether the Pad is controlled by GPIO controller logic or one of the native functions muxed onto the Pad. 0h = GPIO control the Pad |
9 | 0b | RW | GPIO RX Disable (GPIORXDIS) 0 = Enable the input buffer (active low enable) of the pad |
8 | 0b | RW | GPIO TX Disable (GPIOTXDIS) 0 = Enable the output buffer (active low enable) of the pad |
7:2 | - | - | Reserved
|
1 |
| RO/V | GPIO RX State (GPIORXSTATE) This is the current internal RX pad state after Glitch Filter logic stage and hardware debouncer (if any) and is not affected by PMode and RXINV settings. |
0 | 0b | RW | GPIO TX State (GPIOTXSTATE) 0 = Drive a level '0' to the TX output pad |