TCO1_STS Register (TSTS1) – Offset 4 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

Intel® 400 Series Chipset On-Package Platform Controller Hub

Online Register Database

ID	Date	Version	Classification
615146	08/09/2019	1.2	Public

TCO1_STS Register (TSTS1) – Offset 4

Unless otherwise indicated, these bits are sticky and are cleared by writing a 1 to the corresponding bit position.

Bit Range	Default	Access	Field Name and Description
14	-	-	Reserved
13	0b	RO	TCO Slave Select (TCO_SLVSEL) This register bit indicates the value of TCO Slave Select Soft Strap.
12	0b	RW/1C	CPUSERR_STS (CPUSERR_STS) This bit is set to 1 if the CPU complex sends a DMI special cycle message indicating that it wants to cause an SERR#. The software must read the CPU to find out why it wanted the SERR#. Software must write a 1 back to this bit to clear it.
11	-	-	Reserved
10	0b	RW/1C	CPUSMI_STS (CPUSMI_STS) This bit is set to 1 if the CPU complex sends a DMI special cycle message indicating that it wants to cause an SMI. The software must read the CPU to find out why it wanted the SMI. Software must write a 1 back to this bit to clear it.
9	0b	RW/1C	(CPUSCI_STS) This bit is set to 1 if the CPU complex sends a DMI special cycle message indicating that it wants to cause an SCI. The software must read the CPU to find out why it wanted the SCI. Software must write a 1 back to this bit to clear it.
8	0b	RW/1C	(BIOSWR_STS) Intel PCH sets this bit to 1 and generates an SMI# to indicate an illegal attempt to write to the BIOS located in the FWH that is accessed over the LPC. This occurs when either: a) The BIOSWP bit is changed from 0 to 1 and the LE bit is also set, or b) Any write is attempted to the BIOS and the BIOSWP bit is also set. This bit doesn’t get set to 1 when: 1) a or b above occurs on eSPI controller. 2) a or b above occurs on SPI Flash controller. Note: On write cycles attempted to the 4MB lower alias to the BIOS space, the BIOSWR_STS bit will not be set.
7	0b	RW/1C	NEWCENTURY_STS (NEWCENTURY_STS) This bit will be set when the year rolls over from 1999 to 2000. If the bit is already 1, it will remain 1. This bit can be cleared either by software writing a 1 back to the bit position, or by RTCRST# going active. When this bit is set, an SMI# will be generated. However, this will not be a wake event (i.e. if the system is in a sleeping state when the NEWCENTURY_STS bit is set, the system will not wake up). Note: This bit 7 is not valid when the RTC battery is first put in (or if the RTC battery does not provide sufficient power when the system is unplugged). Software can determine that the RTC well was not maintained by checking the RTC_PWR_STS bit (GEN_PMCON_3 register in the Power Management Controller, D31:F2:A4, bit 2) or by other means (such as doing a checksum on the RTC RAM array). If the RTC well is determined to not have been maintained, the BIOS should set the time to a legal value and then clear the NEWCENTURY_STS bit. Note: This bit may take up to 3 RTCCLKs for the bit to be cleared when a 1 is written to the bit to clear it. After writing a 1 to the NEWCENTURY_STS bit, software should also not exit the SMI handler until after the bit has been cleared. This is to make sure the SMI is not re-entered. BIOS Assumption: When booting, the BIOS checks the NEWCENTURY_STS bit. If set, the BIOS should increment the value in the RTC RAM register associated with the century. The BIOS should then clear the NEWCENTURY_STS bit. This scenario would occur if the system was asleep when the century rolls over. If the system is in an S0 state (not sleeping) and the SMI# occurs with the NEWCENTURY_STS bit sets, the SMI handler should increment the value in the RTC RAM register and clear the NEWCENTURY_STS bit.
6:4	-	-	Reserved
3	0b	RW/1C	TIMEOUT (TIMEOUT) Bit set to 1 by Intel PCH to indicate that the SMI was caused by TCO timer reaching 0. Note: The SMI handler should clear this bit to prevent an immediate re-entry to the SMI handler.
2	0b	RW/1C	TCO_INT_STS (TCO_INT_STS) Bit set to 1 when SMI handler caused the interrupt by writing to the TCO_DAT_OUT register.
1	0b	RW/1C	(OS_TCO_SMI) Bit set to 1 when OS code caused an SMI# by writing to the TCO_DAT_IN register.
0	0b	RO/V	(NMI2SMI_STS) The PCH sets this bit when an SMI# occurs because an event occurred that would otherwise have caused an NMI.