DMA Transfer Configuration High (CFG_HI0) – Offset 844 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

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DMA Transfer Configuration High (CFG_HI0) – Offset 844

NOTE: CFG_HI0 is for DMA Channel 0. The same register definition, CFG_HI1, is available for Channel 1 at address 89Ch.

CFG_HI0(CH0): offset 844h

CFG_HI1(CH1): offset 89Ch

This register contains fields that configure the DMA transfer. The channel configuration register remains fixed for all blocks of a multi-block transfer. This Register should be programmed to enabling the channel

Bit Range	Default	Access	Field Name and Description
30:28	-	-	Reserved
27:18	0h	RW	Write Issue Threshold (WR_ISSUE_THD) Write Issue Threshold. Used to relax the issue criterion for Writes. Value ranges from 0 to (2^10-1 = 1023) but should not exceed maximum Write burst size = (2 ^ DST_MSIZE)*TW.
17:8	0h	RW	Read Issue Threshold (RD_ISSUE_THD) Read Issue Threshold. Used to relax the issue criterion for Reads. Value ranges from 0 to (2^10-1 = 1023) but should not exceed maximum Read burst size = (2 ^ SRC_MSIZE)*TW.
7:4	0h	RW	Destination Peripheral ID (DST_PER) Destination Peripheral ID : Assigns a hardware handshaking interface (0 - 15) to the destination of channel n. The channel can then communicate with the destination peripheral connected to that interface through the assigned hardware handshaking interface. NOTE: For correct DMA operation, only one peripheral (source or destination) should be assigned to the same handshaking interface.
3:0	0h	RW	Source Peripheral ID (SRC_PER) Source Peripheral ID : Assigns a hardware handshaking interface (0 - 15) to the source of channel n. The channel can then communicate with the source peripheral connected to that interface through the assigned hardware handshaking interface. NOTE: For correct DMA operation, only one peripheral (source or destination) should be assigned to the same handshaking interface.

Source Gather (SGR0)

DMA Transfer Configuration Low (CFG_LO0) Source Gather (SGR0)