Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_DSW_0) – Offset 84
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
30:12 | - | - | Reserved
|
11 | 0b | RW | Pad Config Lock TXState (PADCFGLOCKTX_GPD_11) Applied to GPD4. Same description as bit 0. |
10 | 0b | RW | Pad Config Lock TXState (PADCFGLOCKTX_GPD_10) Applied to GPD10. Same description as bit 0. |
9 | 0b | RW | Pad Config Lock TXState (PADCFGLOCKTX_GPD_9) Applied to GPD9. Same description as bit 0. |
8 | 0b | RW | Pad Config Lock TXState (PADCFGLOCKTX_GPD_8) Applied to GPD8. Same description as bit 0. |
7 | 0b | RW | Pad Config Lock TXState (PADCFGLOCKTX_GPD_7) Applied to GPD7. Same description as bit 0. |
6 | 0b | RW | Pad Config Lock TXState (PADCFGLOCKTX_GPD_6) Applied to GPD6. Same description as bit 0. |
5 | 0b | RW | Pad Config Lock TXState (PADCFGLOCKTX_GPD_5) Applied to GPD5. Same description as bit 0. |
4 | 0b | RW | Pad Config Lock TXState (PADCFGLOCKTX_GPD_4) Applied to GPD4. Same description as bit 0. |
3 | 0b | RW | Pad Config Lock TXState (PADCFGLOCKTX_GPD_3) Applied to GPD3. Same description as bit 0. |
2 | 0b | RW | Pad Config Lock TXState (PADCFGLOCKTX_GPD_2) Applied to GPD2. Same description as bit 0. |
1 | 0b | RW | Pad Config Lock TXState (PADCFGLOCKTX_GPD_1) Applied to GPD1. Same description as bit 0. |
0 | 0b | RW | Pad Config Lock TXState (PADCFGLOCKTX_GPD_0) PadCfgLockTx locks the GPIOTxState bit from being configured. The GPIOTxState register becomes Read-Only and software writes to the register have no effect. |