Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
Power Gating Control (PGCTL) – Offset 44
D3PGD are meant for the Intel HD Audio driver software to control whether the Intel HD Audio subsystem should be power gated or not in D3.
Note that the power gating will only be initiated when out of platform reset, if conditions are met.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
30:5 | - | - | Reserved
|
4 | 0b | RW | LP SRAM Retention Module Disable (LSRMD) Register is used to disable the LP SRAM retention mode capbility of the |
3 | 0b | RW | HP SRAM Retention Module Disable (HSRMD) Register is used to disable the HP SRAM retention mode capbility of the |
2 | - | - | Reserved
|
1 | 0b | RW | D3 Power Gating Disable (CTLPGD) Register is used to disable the power gating capbility during D3 state. |
0 | 0b | RW | Low Power Audio Power Gating Disable (LPAPGD) Register is used to disable the power gating capbility of the Primary well |