Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
Strap Configuration 1 (STRPFUSECFG1) – Offset 200
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31 | 0b | RO/V | GbE Over PCI Express Port Enable Strap (GBE_PCIE_PEN) 0 : GbE MAC/PHY port communication is not enabled over PCI Express. |
30:28 | 000b | RO/V | GBE PCIe Port Select Strap (GBE_PCIEPORTSEL) Used to determine which PCIe port to be used for GbE MAC/PHY over PCI Express communication. |
27:24 | - | - | Reserved
|
23:8 | 0000h | RO/V | PCIe/SATA Combo Port Select Polarity (PSCPSP) 0: When the Combo Port Select pin is '0, PCIe mode is selected. When the Combo Port Select pin is '1, SATA mode is selected. |
7:2 | - | - | Reserved
|
1 | 0b | RO/V | Core Dynamic Clock Gating Disable (CDCGDIS) 0: Core dynamic clock gating enabled. |
0 | 0b | RO/V | HSIO Power Gating Disabled (MPGD) 0b: HSIO power gating capability is enabled. |