Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
I2C Rx/Tx Data Buffer and Command (IC_DATA_CMD) – Offset 10
This register is used by the processor to write to when filling the Tx FIFO and to readfrom when retrieving bytes form Tx FIFO. In order for the I2C controller to continueacknowledging reads, a read command should be written for every byte that is to bereceived; otherwise, the controller will stop acknowledging.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
30:11 | - | - | Reserved
|
10 | 0h | RW | Restart (RESTART) This bit controls whether a RESTART is issued before the byte is sent or received. |
9 | 0h | RW | Stop (STOP) This bit controls whether a STOP is issued after the byte is sent or received. |
8 | 0h | RW | Command (CMD) This bit controls whether a read or a write is performed. |
7:0 | 0h | RW | Data (DAT) This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the I2C. However, when you read this register, these bits return the value of data received on the I2C interface. |