Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
Power Management Status and Control (CNVI_WIFI_PMCSR) – Offset cc
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:24 | 0xd | RO | PWR_DIS_CON (PWR_DIS_CON) used to report power consumption and heat dissipation (default for D3-0x1) |
23 | 0x0 | RO | BUS_PWR_CLK_CEN (BUS_PWR_CLK_CEN) Bus Power/Clock Control Enable. Does not apply. Hardwired to 0. |
22 | 0x0 | RO | B2_B3_SUPRT (B2_B3_SUPRT) B2/B3 Support. Does not apply. Hardwired to 0. |
21:16 | - | - | Reserved
|
15 | 0x0 | RW/1C | PME_STAT (PME_STAT) This bit reflects whether the function has experienced a PME. sticky value. |
14:13 | 0x0 | RO | DAT_SCALE (DAT_SCALE) Data Scale |
12:9 | 0x0 | RW | DAT_SEL (DAT_SEL) Data Select, selects the data value to be viewed through the Data register |
8 | 0x0 | RW | PME_ENA (PME_ENA) PME Enable. sticky value. |
7:4 | - | - | Reserved
|
3 | 0x1 | RO | NO_SOFT_RESET (NO_SOFT_RESET) No_Soft_Reset |
2 | - | - | Reserved
|
1:0 | 0x0 | RW | PWR_STATE (PWR_STATE) Power State |