DMI Control Register (DMIC) – Offset 2234 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

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8254 Timer
Advanced Programmable Interrupt Controller (APIC)
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CNVi PCI Configuration
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xHCI Configuration
xHCI Memory Mapped

DMI Control Register (DMIC) – Offset 2234

Offset 2234h: DMIC DMI Control Register (Common)

Bit Range	Default	Access	Field Name and Description
31	0b	RW/L	Secured Register Lock (SRL) When this bit is set, all the secured registers will be locked and will be Read-Only.
30:5	-	-	Reserved
4	0b	RW	Partition/Trunk Oscillator Clock Gate Enable (PTOCGE) When set, this bit allows the oscillator clock to be gated at the partition/trunk level when the conditions are met. When cleared, the oscillator clock gating at the partition/trunk level is disabled.
3	0b	RW	DMI Link CLKREQ Enable (DMILCLKREQEN) When set, this bit enables DMI to de-assert the DMI link CLKREQ. When cleared, DMI link CLKREQ is not allowed to de-assert.
2	0b	RW	DMI Backbone CLKREQ Enable (DMIBBCLKREQEN) When set, this bit enables DMI to de-assert the Primary backbone CLKREQ. When cleared, DMI Primary backbone CLKREQ is not allowed to de-assert.
1	0b	RW	DMI Link Dynamic Clock Gate Enable (DMILCGEN) When set, this bit enables dynamic clock gating on the DMI Link clock domain logic. When cleared, dynamic clock gating on the DMI Link clock domain is disabled.
0	0b	RW	DMI Backbone Dynamic Clock Gate Enable (DMIBCGEN) When set, this bit enables dynamic clock gating on the DMI backbone domain logic. When cleared, dynamic clock gating on the DMI backbone clock domain is disabled.

IOSF Primary Control And Status (IPCS_IOSFSBCS)

Error Source Identification (ESID) IOSF Primary Control And Status (IPCS_IOSFSBCS)