Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
Device Capabilities (CNVI_WIFI_GIO_DEV_CAP) – Offset 44
The Device Capabilities register identifies PCI Express device specific capabilities.(Offset 044 h)
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
30:29 | - | - | Reserved
|
28 | 0x1 | RO | Function Level Reset Capability (FUNC_LVL_RES)
|
27:26 | 0x0 | RO | Slot Power Limit Scale (SLT_PW_LSCL) Captured Slot Power Limit Scale |
25:18 | 0x0 | RO | Slot Power Limit Value (SLT_PW_LVAL) Captured Slot Power Limit Value |
17:16 | - | - | Reserved
|
15 | 0x0 | RO | Error Reporting Support (ROLE_BASED_ERR) This field indicates that the device supports Error reporting. |
14:12 | - | - | Reserved
|
11:9 | 0x7 | RO | Endpoint L1 Acceptable Latency (L1_ACC_LAT)
|
8:6 | 0x3 | RO | Endpoint L0s Acceptable Latency (L0S_ACC_LAT)
|
5 | 0x0 | RO | Extended Tag Field Supported (EX_TAG_FIELD)
|
4:3 | - | - | Reserved
|
2:0 | 0x0 | RO | Max Payload Size Supported (MAX_PL_SIZE)
|