Device Control; Device Status (DCTL_DSTS) – Offset 48 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

Intel® 400 Series Chipset On-Package Platform Controller Hub

Online Register Database

ID	Date	Version	Classification
615146	08/09/2019	1.2	Public

Device Control; Device Status (DCTL_DSTS) – Offset 48

Bit Range	Default	Access	Field Name and Description
30:22	-	-	Reserved
21	0b	RO	Transactions Pending (TDP) This bit has no meaning for the root port since it never initiates a non-posted request with its own Requester ID.
20	1b	RO	AUX Power Detected (APD) The root port contains AUX power for wakeup
19	0b	RW/1C/V	Unsupported Request Detected (URD) Indicates an unsupported request was detected.
18	0b	RW/1C/V	Fatal Error Detected (FED) Indicates a fatal error was detected. Set when a fatal error occurred on from a data link protocol error, buffer overflow, or malformed tlp
17	0b	RW/1C/V	Non-Fatal Error Detected (NFED) Indicates a non-fatal error was detected. Set when an received a non-fatal error occurred from a poisoned tlp, unexpected completions, unsupported requests, completor abort, or completer timeout
16	0b	RW/1C/V	Correctable Error Detected (CED) Indicates a correctable error was detected. Set when received an internal correctable error from receiver errors / framing errors, tlp crc error, dllp crc error, replay num rollover, replay timeout.
15	-	-	Reserved
14:12	000b	RO	Max Read Request Size (MRRS) Hardwired to 0. This field applies only to the PCIe link interface.
11	0b	RO	Enable No Snoop (ENS) Not supported. The root port will never issue non-snoop requests.
10	0b	RW/P	Aux Power PM Enable (APME) The OS will set this bit to '1 if the device connected has detected aux power.
9	0b	RO	Phantom Functions Enable (PFE) Not supported
8	0b	RO	Extended Tag Field Enable (ETFE) Not supported
7:5	000b	RW	Max Payload Size (MPS) The root port only supports up to 256B max payload. Programming this field to any values other than 128B or 256B max payload size will result in aliasing to 128B max payload size. If the DCAP.MPS indicates 128B max payload size support, programming this field to any values other than 128B will result in aliasing to 128B max payload size. Programming this field to any values greater than DCAP.MPS will result in aliasing to 128B max payload size. 000b: 128 bytes max payload size. 001b: 256 bytes max payload size. 010b: 512 bytes max payload size. 011b: 1024 bytes max payload size. 100b: 2048 bytes max payload size. 101b: 4096 bytes max payload size. 110b: Reserved. 111b: Reserved. This field applies only to the PCIe link interface. Note: Software should ensure that the system is quiescent and no TLP is in progress prior to changing this field. BIOS should program this field prior to enabling BME.
4	0b	RO	Enable Relaxed Ordering (ERO) Not supported
3	0b	RW	Unsupported Request Reporting Enable (URE) When set, allows signaling ERR_NONFATAL, ERR_FATAL, or ERR_COR to the Root Control register when detecting an unmasked Unsupported Request (UR). An ERR_COR is signaled when a unmasked Advisory Non-Fatal UR is received. An ERR_FATAL, ERR_or NONFATAL, is sent to the Root Control Register when an uncorrectable non-Advisory UR is received with the severity set by the Uncorrectable Error Severity register.
2	0b	RW	Fatal Error Reporting Enable (FEE) enables signaling of ERR_FATAL to the Root Control register due to internally detected errors or error messages received across the link. Other bits also control the full scope of related error reporting.
1	0b	RW	Non-Fatal Error Reporting Enable (NFE) When set, enables signaling of ERR_NONFATAL to the Root Control register due to internally detected errors or error messages received across the link. Other bits also control the full scope of related error reporting.
0	0b	RW	Correctable Error Reporting Enable (CEE) When set, enables signaling of ERR_CORR to the Root Control register due to internally detected errors or error messages received across the link. Other bits also control the full scope of related error reporting.