Capability Parameters (HCCPARAMS) – Offset 10 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

Intel® 400 Series Chipset On-Package Platform Controller Hub

Online Register Database

ID	Date	Version	Classification
615146	08/09/2019	1.2	Public

Capability Parameters (HCCPARAMS) – Offset 10

This register is modified and maintained by BIOS

Bit Range	Default	Access	Field Name and Description
31:16	2000h	RW/L	xHCI Extended Capabilities Pointer (xECP) This field indicates the existence of a capabilities list. The value of this field indicates a relative offset, in 32-bit words, from Base to the beginning of the first extended capability.
15:12	7h	RW/L	Maximum Primary Stream Array Size (MaxPSASize) RW/L. This fields identifies the maximum size Primary Stream Array that the xHC supports. The Primary Stream Array size = 2MaxPSASize+1. Valid MaxPSASize values are 1 to 15.
11	0h	RW/L	Contiguous Frame ID Capability (CFC)
10	1h	RW/L	Stopped EDLTA Capabilty (SEC) This flag indicates that the host controller implementation Stream Context support a Stopped EDLTA field.
9	1h	RW/L	Stopped - Short Packet Capability (SPC) This flag indicates that the host controller implementation is capable of generating a Stopped-Short Packet Completion Code.
8	1b	RW/L	Parst All Event Data (PAE)
7	1b	RW/L	No Secondary SID Support (NSS) Hardwired to ‘0’ indicating Secondary Stream ID decoding is supported.
6	1b	RW/L	Latency Tolerance Messaging Capability (LTC) 0 = Latency Tolerance Messaging is not supported. 1 = Latency Tolerance Messaging is supported
5	0b	RW/L	Light HC Reset Capability (LHRC) 0 = Light Host Controller Reset is not supported. 1 = Light Host Controller Reset is supported
4	0b	RW/L	Port Indicators (PIND) This bit indicates whether the xHC root hub ports support port indicator control. When this bit is a ‘1’, the port status and control registers include a read/writeable field for controlling the state of the port indicator.
3	0b	RW/L	Port Power Control (PPC) This bit indicates whether the host controller implementation includes port power control. A ‘1’ in this bit indicates the ports have port power switches. A ‘0’ in this bit indicates the port do not have port power switches.
2	0b	RW/L	Context Size (CSZ) If this bit is set to ‘1’, then the xHC uses 64 byte Context data structures. If this bit is cleared to ‘0’, then the xHC uses 32 byte Context data structures.
1	0b	RW/L	BW Negotiation Capability (BNC) 0 = Not capable of BW Negotiation. 1 = Capable of BW Negotiation.
0	1b	RW/L	64-bit Addressing Capability (AC64) This bit documents the addressing range capability of the xHC. The value of this flag determines whether the xHC has implemented the high order 32- bits of 64-bit register and data structure pointer fields. Values for this flag have the following interpretation: 0 = Supports 32-bit address memory pointers 1 = Supports 64-bit address memory pointers If 32-bit address memory pointers are implemented, the xHC shall ignore the high order 32- bits of 64-bit data structure pointer fields, and system software shall ignore the high order 32- bits of 64- bit xHC registers.