HOST_CTRL_MISC_REG (HOST_CTRL_MISC_REG) – Offset 80b0 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

Intel® 400 Series Chipset On-Package Platform Controller Hub

Online Register Database

ID	Date	Version	Classification
615146	08/09/2019	1.2	Public

HOST_CTRL_MISC_REG (HOST_CTRL_MISC_REG) – Offset 80b0

Bit Range	Default	Access	Field Name and Description
31	0b	RW	USB2_LTRUPDT_DIS (USB2_LTRUPDT_DIS)
30	0b	RW	USB2 Line State Debounce During Port Reset Policy (USB2_LINE_STATE_DEBOUNCE_DURING_PORT_RESET_POLICY) This register controls how the debounce is enforced during the Port Reset phase. 0 do not enable the line state debounce during port reset. 1 enable the line state debounce during port reset.
29	0b	RW	TTE PEXE Credit Fix Disable (TTE_PEXE_CREDIT_FIX_DISABLE) When set, it disables a fix implemented to re-deem PEXE credits when a port is disconnected
28	0b	RW	TTE Scheduling policy (TTE_SCHEDULING_POLICY) This register controls a fix made to prevent over-scheduling by not account for 188B in each uFrame. Setting this bit will disable the fix and allow for over-scheduling.
27	0b	RW	USB3 ITP Delta Timer Source Select (USB3_ITP_DELTA_TIMER_SOURCE_SELECT) This register selects the source for the delta timer tracking used for ITP generation. 0 the source is a 16.666 ns tick generated from a crystal reference clock 1 - the source is a 16.666 ns tick generated from the aux_cclk. This field needs to remain in sync with Frame Timer Source Select to ensure the are both set or both cleared. There is no support for any other combination.
26	0b	RW	Frame Timer Source Select (FRAME_TIMER_SOURCE_SELECT) This register controls the source for the frame timer. 0 the source for the frame timer is a crystal reference clock 1 the source for the frame timer is the aux_cclk.
25	0b	RW	uFrame Masking Enable (UFRAME_MASKING_ENABLE) If set, enables the uFrame tick to be masked due to ports being in U3/NC. This controls a fix made to disable the auto masking of uFrame tick due to port state w/o any pipeline idle condition. When cleared, we rely on gating of frame timer due to proper port state and idleness tracking from the pipeline.
24	0b	RW	Late FID Check Disable (LATE_FID_CHECK_DISABLE) This register disables the Late FID Check performed when starting an ISOCH stream.
23:20	-	-	Reserved
19	0h	RW	USB2 Resume Cx Inhibit Disable (USB2_RESUME_CX_INHIBIT_DISABLE) Controls if USB2 L1 Resume is allowed to contribute to DMA Active which will inhibit Cx state. 0 USB2 L1 Resume is allowed to inhibit Cx via DMA Active 1 USB2 L1 Resume is NOT allowed to inhibit Cx via DMA Active When cleared, Cx will only be inhibited when the DMA traffic for the port begins.
18	0h	RW	(LATE_FID_TTE_DIS) Late FID TTE Disable 0: Late Frame ID Check is enabled for TTE Endpoints 1: Late Frame ID Check is disabled for TTE Endpoints
17	0h	RW	Late FID uframe Check Disable (LATE_FID_UFRAME_CHK_DIS) 0 Frame ID Match only asserts in uframe 7 for non-TTE Endpoints Frame before match 1 Frame ID Match can assert in any uframe
16	1h	RW	Late FID Extra Interval (LATE_FID_EXTRA_INTER) This register controls the extra number of intervals added onto the advancing of late FID check escentially a bias used to correct for possible errors in implementation
15:0	037Fh	RW	Valid Isoch Scheduling Range (VALID_ISOCH_SCHEDULING_RANGE) This register defines the window in miliseconds from the current Frame that will be considered for scheduling in an upcoming Frame. Anything scheduled outside of this window will be considered as late and will trigger the Missed Service Error.