Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
| ID | Date | Version | Classification |
|---|---|---|---|
| 615146 | 08/09/2019 | 1.2 | Public |
Introduction
8254 Timer
Advanced Programmable Interrupt Controller (APIC)
APIC Indirect
CNVi PCI Configuration
DCI PCR
EMMC Additional
EMMC Memory Mapped
EMMC PCI Configuration
eMMC PCR
Enhanced SPI (eSPI) PCI Configuration
eSPI PCR
FIA Configuration PCR
GbE Configuration
GbE Memory Mapped I/O
Generic SPI (GSPI) Additional
Generic SPI (GSPI) DMA Controller
Generic SPI (GSPI) Memory Mapped
GPIO Community 0
GPIO Community 1
GPIO Community 2
GPIO Community 3
GPIO Community 4
GSPI PCI Configuration
High Definition Audio (D31:F3) Memory Mapped I/O
High Definition Audio (D31:F3) PCI Configuration
HPET Memory Mapped
I2C Additional
I2C DMA Controller
I2C Memory Mapped
I2C PCI Congifuration
IDE Redirect PCI Configuration (D22:F2)
Integrated Clock (ICC) Configuration
Intel RST for PCIe Storage (Remapping) PCI Configuration (D24:F0)
Intel RST for PCIe Storage MMIO
Intel(R) Management Engine Interface PCI Configuration
Intel(R) MEI MMIO
Intel(R) Trace Hub Configuration
Intel® HD Audio PCR
Interrupt
Interrupt PCR
IO Trap
ISH
ISH PCH Configuration
ISH PCR
Keyboard and Text (KT) Additional Configuration
Keyboard and Text (KT) PCI Configuration (D22:F3)
LPC Configuration
LPC PCR
OPI PCR
P2SB PCI Configuration
PCI Express* Port Configuration
PMC I/O Based
PMC Memory Mapped
PMC SSRAM PCI Configuration
Power Management Configuration
Processor Interface Memory
PSF1
PSF2
PSF3
PSF4
PSF5
RTC Indexed
RTC PCR
SATA ABAR
SATA AIDP
SATA Configuration
SATA Initialization (SIR) Index
SATA MXPBA
SATA MXTBA
SDXC (SD Card) PCR
SDXC Additional Memory Mapped
SDXC Memory Mapped
SDXC PCI Configuration
SMBus Configuration
SMBus I/O and Memory Mapped I/O
SMBus PCR
SMBus TCO I/O
SPI Configuration
SPI Memory Mapped
Thermal Reporting Configuration
Thermal Reporting Memory Mapped
UART Additional Memory Mapped
UART DMA Controller
UART Memory Mapped
UART PCI Configuration
xDCI MMIO Device
xDCI MMIO Global
xDCI PCI Configuration
xHCI Configuration
xHCI Memory Mapped
8254 Timer
Counter 0 - Interval Timer Status Byte Format Register (C0_ITSBFR)
Counter 2 - Interval Timer Status Byte Format Register (C2_ITSBFR)
Timer Control Word Register (TCW)
Counter 0 - Counter Access Ports Register (C0_CAPR)
Counter 2 - Counter Access Ports Register (C2_CAPR)
Read Back Command (RBC)
Counter Latch Command (CLC)
APIC Indirect
Identification Register (ID)
Version Register (VER)
Redirection Table Entry 0 (RTE0)
Redirection Table Entry 1 (RTE1)
Redirection Table Entry 2 (RTE2)
Redirection Table Entry 3 (RTE3)
Redirection Table Entry 4 (RTE4)
Redirection Table Entry 5 (RTE5)
Redirection Table Entry 6 (RTE6)
Redirection Table Entry 7 (RTE7)
Redirection Table Entry 8 (RTE8)
Redirection Table Entry 9 (RTE9)
Redirection Table Entry 10 (RTE10)
Redirection Table Entry 11 (RTE11)
Redirection Table Entry 12 (RTE12)
Redirection Table Entry 13 (RTE13)
Redirection Table Entry 14 (RTE14)
Redirection Table Entry 15 (RTE15)
Redirection Table Entry 16 (RTE16)
Redirection Table Entry 17 (RTE17)
Redirection Table Entry 18 (RTE18)
Redirection Table Entry 19 (RTE19)
Redirection Table Entry 20 (RTE20)
Redirection Table Entry 21 (RTE21)
Redirection Table Entry 22 (RTE22)
Redirection Table Entry 23 (RTE23)
Redirection Table Entry 24 (RTE24)
Redirection Table Entry 25 (RTE25)
Redirection Table Entry 26 (RTE26)
Redirection Table Entry 27 (RTE27)
Redirection Table Entry 28 (RTE28)
Redirection Table Entry 29 (RTE29)
Redirection Table Entry 30 (RTE30)
Redirection Table Entry 31 (RTE31)
Redirection Table Entry 32 (RTE32)
Redirection Table Entry 33 (RTE33)
Redirection Table Entry 34 (RTE34)
Redirection Table Entry 35 (RTE35)
Redirection Table Entry 36 (RTE36)
Redirection Table Entry 37 (RTE37)
Redirection Table Entry 38 (RTE38)
Redirection Table Entry 39 (RTE39)
Redirection Table Entry 40 (RTE40)
Redirection Table Entry 41 (RTE41)
Redirection Table Entry 42 (RTE42)
Redirection Table Entry 43 (RTE43)
Redirection Table Entry 44 (RTE44)
Redirection Table Entry 45 (RTE45)
Redirection Table Entry 46 (RTE46)
Redirection Table Entry 47 (RTE47)
Redirection Table Entry 48 (RTE48)
Redirection Table Entry 49 (RTE49)
Redirection Table Entry 50 (RTE50)
Redirection Table Entry 51 (RTE51)
Redirection Table Entry 52 (RTE52)
Redirection Table Entry 53 (RTE53)
Redirection Table Entry 54 (RTE54)
Redirection Table Entry 55 (RTE55)
Redirection Table Entry 56 (RTE56)
Redirection Table Entry 57 (RTE57)
Redirection Table Entry 58 (RTE58)
Redirection Table Entry 59 (RTE59)
Redirection Table Entry 60 (RTE60)
Redirection Table Entry 61 (RTE61)
Redirection Table Entry 62 (RTE62)
Redirection Table Entry 63 (RTE63)
Redirection Table Entry 64 (RTE64)
Redirection Table Entry 65 (RTE65)
Redirection Table Entry 66 (RTE66)
Redirection Table Entry 67 (RTE67)
Redirection Table Entry 68 (RTE68)
Redirection Table Entry 69 (RTE69)
Redirection Table Entry 70 (RTE70)
Redirection Table Entry 71 (RTE71)
Redirection Table Entry 72 (RTE72)
Redirection Table Entry 73 (RTE73)
Redirection Table Entry 74 (RTE74)
Redirection Table Entry 75 (RTE75)
Redirection Table Entry 76 (RTE76)
Redirection Table Entry 77 (RTE77)
Redirection Table Entry 78 (RTE78)
Redirection Table Entry 79 (RTE79)
Redirection Table Entry 80 (RTE80)
Redirection Table Entry 81 (RTE81)
Redirection Table Entry 82 (RTE82)
Redirection Table Entry 83 (RTE83)
Redirection Table Entry 84 (RTE84)
Redirection Table Entry 85 (RTE85)
Redirection Table Entry 86 (RTE86)
Redirection Table Entry 87 (RTE87)
Redirection Table Entry 88 (RTE88)
Redirection Table Entry 89 (RTE89)
Redirection Table Entry 90 (RTE90)
Redirection Table Entry 91 (RTE91)
Redirection Table Entry 92 (RTE92)
Redirection Table Entry 93 (RTE93)
Redirection Table Entry 94 (RTE94)
Redirection Table Entry 95 (RTE95)
Redirection Table Entry 96 (RTE96)
Redirection Table Entry 97 (RTE97)
Redirection Table Entry 98 (RTE98)
Redirection Table Entry 99 (RTE99)
Redirection Table Entry 100 (RTE100)
Redirection Table Entry 101 (RTE101)
Redirection Table Entry 102 (RTE102)
Redirection Table Entry 103 (RTE103)
Redirection Table Entry 104 (RTE104)
Redirection Table Entry 105 (RTE105)
Redirection Table Entry 106 (RTE106)
Redirection Table Entry 107 (RTE107)
Redirection Table Entry 108 (RTE108)
Redirection Table Entry 109 (RTE109)
Redirection Table Entry 110 (RTE110)
Redirection Table Entry 111 (RTE111)
Redirection Table Entry 112 (RTE112)
Redirection Table Entry 113 (RTE113)
Redirection Table Entry 114 (RTE114)
Redirection Table Entry 115 (RTE115)
Redirection Table Entry 116 (RTE116)
Redirection Table Entry 117 (RTE117)
Redirection Table Entry 118 (RTE118)
Redirection Table Entry 119 (RTE119)
CNVi PCI Configuration
Vendor and Device ID (CNVI_WIFI_VEN_DEV_ID)
Device Command and Status (CNVI_WIFI_PCI_COM_STAT)
Class Code and Revision ID (CNVI_WIFI_PCI_CLASS_CODE)
Base Address Register BAR0 Low (CNVI_WIFI_BAR0)
Base Address Register BAR0 High (CNVI_WIFI_BAR1)
Subsystem ID (CNVI_WIFI_SUBSYS_ID)
Capabilities Pointer (CNVI_WIFI_CAP_PTR)
Interrupt (CNVI_WIFI_INTERRUPT)
PCI Express Capabilities (CNVI_WIFI_GIO_CAP)
Device Capabilities (CNVI_WIFI_GIO_DEV_CAP)
Device Control Register (CNVI_WIFI_GIO_DEV)
Device Control 2 (CNVI_WIFI_GIO_DEV_CAP_2)
Device Control (CNVI_WIFI_GIO_DEV_2)
MSIX Capability (CNVI_WIFI_MSIX_CAP_HEAD)
MSIX Capability Structure (CNVI_WIFI_MSIX_TABLE_OFFSET)
MSIX Capability Structure (CNVI_WIFI_MSIX_PBA_OFFSET)
Power Management Capabilities (CNVI_WIFI_PMC)
Power Management Status and Control (CNVI_WIFI_PMCSR)
Capability ID and Message Control (CNVI_WIFI_MSI_MSG_CTRL)
MSI Low Address (CNVI_WIFI_MSI_LOW_ADD)
MSI High Address (CNVI_WIFI_MSI_HIGH_ADD)
MSI Data (CNVI_WIFI_MSI_DATA)
Uncorrectable Error Status Register (CNVI_WIFI_UNCORRECT_ERR_STAT)
Uncorrectable Error mask Register (CNVI_WIFI_UNCORRECT_ERR_MASK)
Uncorrectable Error Severity (CNVI_WIFI_UNCORRECT_ERR_SEV)
Error Status (CNVI_WIFI_CORRECT_ERR_STAT)
Error Mask (CNVI_WIFI_CORRECT_ERR_MASK)
Advanced Error Capabilities and Control (CNVI_WIFI_ADVANCED_ERR_CAP)
Header Log 1 (CNVI_WIFI_HEADER_LOG1)
Header Log 2 (CNVI_WIFI_HEADER_LOG2)
Header Log 3 (CNVI_WIFI_HEADER_LOG3)
Header Log 4 (CNVI_WIFI_HEADER_LOG4)
Device Serial Number Capability (CNVI_WIFI_GIO_SERIAL_CAP)
Serial Number Low (CNVI_WIFI_GIO_SERIAL_LOW)
Serial Number Upper (CNVI_WIFI_GIO_SERIAL_UP)
Header of LTR Extended Capability (CNVI_WIFI_LTR_EXTND_CAP_HEAD)
No Snoop Request (CNVI_WIFI_LTR_MAX_SNOOP_NOSNOOP_LAT)
L1 substates Extended Capability Header (CNVI_WIFI_L1PM_SUB_EXTND_CAP_HEAD)
L1 Substates Capability (CNVI_WIFI_L1PM_SUB_CAP)
L1 Substates Control (CNVI_WIFI_L1PM_SUB_CNTRL)
L1 Substates Control 2 (CNVI_WIFI_L1PM_SUB_CNTRL2)
Vendor Specific Capability Header (CNVI_WIFI_VEN_SPEC_CAP)
Vendor Specific Extended Capability (CNVI_WIFI_VEN_SPEC_EXTND_CAP)
SW LTR Pointer (CNVI_WIFI_LTP_PTR)
DevIdle Pointer (CNVI_WIFI_DEV_IDLE_PTR)
DevIdle Power on Latency (CNVI_WIFI_DEV_IDLE_PWR)
EMMC Additional
Software LTR Value (SW_LTR_val)
Auto LTR Value (Auto_LTR_val)
Capabilities Bypass (Cap_byps)
Capabilities Bypass 1 (Cap_byps_reg1)
Capabilities Bypass Register II (Cap_byps_reg2)
Device Idle D0i3 (reg_D0i3)
Tx CMD Delay Control (Tx_CMD_dly)
Tx Delay Control 1 (Tx_DATA_dly_1)
Tx Delay Control 2 (Tx_DATA_dly_2)
Rx CMD Data Delay Control 1 (Rx_CMD_Data_dly_1)
Rx Strobe Delay Control (Rx_Strobe_Ctrl_Path)
Rx CMD Data Path Delay Control 2 (Rx_CMD_Data_dly_2)
Master DLL Software Control (Master_Dll)
Auto Tuning Value (Auto_tuning)
EMMC Memory Mapped
SDMA System Address (sdmasysaddr)
Block Size (blocksize)
Block Count Register (blockcount)
Argument 1 (argument1)
Transfer Mode Register (transfermode)
Command (command)
Response (Response 0 And 1)
Response 2 (response2)
Response 3 (response3)
Response 4 (response4)
Response 5 (response5)
Response 6 (response6)
Response 6 (response7)
Buffer Data Port Register (dataport)
Present State (PRESENTSTATE)
Host Control 1 (hostcontrol1)
Power Control Register (powercontrol)
Block Gap Control Register (blockgapcontrol)
Wakeup Control (wakeupcontrol)
Clock Control (clockcontrol)
Timeout Control (timeoutcontrol)
Software Reset (softwarereset)
Normal Interrupt Status (normalintrsts)
Error Interrupt Status (errorintrsts)
Normal Interrupt Status Enable (normalintrstsena)
Error Interrupt Status Enable (errorintrstsena)
Normal Interrupt Signal Enable (normalintrsigena)
Error Interrupt Signal Enable (errorintrsigena)
Auto CMD12 Error Status (autocmderrsts)
Host Control 2 (hostcontrol2)
Capabilities (capabilities)
Maximum Current Capabilities (maxcurrentcap)
Force Event for AUTO CMD Error Status (ForceEventforAUTOCMDErrorStatus)
Force Event Register for Error Interrupt Status (forceeventforerrintsts)
ADMA Error Status (admaerrsts)
ADMA System Address Register 1 (admasysaddr01)
ADMA System Address Register2 (admasysaddr2)
Preset Value for Initialization (presetvalue0)
Preset Value for Default Speed (presetvalue1)
Preset Value for High Speed (presetvalue2)
Preset Value for SDR12 (presetvalue3)
Preset Value for SDR25 (presetvalue4)
Preset Value for SDR50 (presetvalue5)
Preset Value for SDR104 (presetvalue6)
Preset Value for DDR50 (presetvalue7)
Boot Timeout Control (boottimeoutcnt)
Slot Interrupt Status (slotintrsts)
EMMC PCI Configuration
Device & Vendor ID (DEVVENDID)
PCI Status & Command (STATUSCOMMAND)
Rev ID & Class Code (REVCLASSCODE)
Carche Line & Latency & Header Type & BIST (CLLATHEADERBIST)
Base Address Low (BAR0)
Base Address Register high (BAR0_HIGH)
Base Address Register1 (BAR1)
(BAR1_HIGH)
Subsystem Vendor ID (SUBSYSTEMID)
(EXPANSION_ROM_BASEADDR)
Capabilities Pointer (CAPABILITYPTR)
Interrupt (INTERRUPTREG)
Power Management Capability ID Register (POWERCAPID)
Power Management Control and Status Register (PMECTRLSTATUS)
PCI Device Idle Capability Record (PCIDEVIDLE_CAP_RECORD)
Device Vendor Specific (DEVID_VEND_SPECIFIC_REG)
SW LTR update MMIO Location Register (D0I3_CONTROL_SW_LTR_MMIO_REG)
Device IDLE Pointer Register (DEVICE_IDLE_POINTER_REG)
DOI3 Max Power & PG Config (D0I3_MAX_POW_LAT_PG_CONFIG)
General Purpose PCI RW Register1 (GEN_REGRW1)
General Purpose PCI RW Register2 (GEN_REGRW2)
General Purpose PCI RW Register3 (GEN_REGRW3)
General Purpose PCI RW Register4 (GEN_REGRW4)
General Input Register (GEN_INPUT_REG)
Enhanced SPI (eSPI) PCI Configuration
Identifiers (ESPI_DID_VID)
Device Status and Command (ESPI_STS_CMD)
Class Code and Revision ID (ESPI_CC_RID)
Sub System Identifiers (ESPI_SS)
Capability List Pointer (ESPI_CAPP)
I/O Decode Ranges and I/O Enables (ESPI_IOD_IOE)
eSPI Generic I/O Range 1 (ESPI_LGIR1)
eSPI Generic I/O Range 2 (ESPI_LGIR2)
eSPI Generic I/O Range 3 (ESPI_LGIR3)
eSPI Generic I/O Range 4 (ESPI_LGIR4)
USB Legacy Keyboard/Mouse Control (ESPI_ULKMC)
eSPI Generic Memory Range (ESPI_LGMR)
BIOS Decode Enable (ESPI_BDE)
BIOS Control (ESPI_BC)
eSPI PCR
eSPI Slave Configuration Register And Link Control (SLV_CFG_REG_CTL)
eSPI Slave Configuration Register Data (SLV_CFG_REG_DATA)
Peripheral Channel Error for Slave 0 (PCERR_SLV0)
Virtual Wire Channel Error for Slave 0 (VWERR_SLV0)
Flash Access Channel Error for Slave 0 (FCERR_SLV0)
Link Error for Slave 0 (LNKERR_SLV0)
FIA Configuration PCR
Common Control (CC)
PCIe* Device Reference Clock Request Mapping 1 (DRCRM1)
PCIe* Device Reference Clock Request Mapping 2 (DRCRM2)
Device Reference Clock Request Mapping 3 (DRCRM3)
Strap Configuration 1 (STRPFUSECFG1)
HSIO Lane Owner Status 1 (LOS1)
HSIO Lane Owner Status 2 (LOS2)
GbE Configuration
GbE Vendor and Device Identification Register (GBE_VID_DID)
PCI Command & Status Register (PCICMD_STS)
Revision Identification & Class Code Register (RID_CC)
Cache Line Size Primary Latency Timer & Header Type Register (CLS_PLT_HEADTYP)
Memory Base Address Register A (MBARA)
Subsystem Vendor & Subsytem ID (DMI_CONFIG11)
Expansion ROM Base Address Register (ERBA)
Capabilities List Pointer Register (CAPP)
Interrupt Information & Maximum Latency/Minimum GrantRegister (INTR_MLMG)
LAN Disable Control (LANDISCTRL)
Lock LAN Disable (LOCKLANDIS)
System Time Control High Register (LTRCAP)
Capabilities List and Power Managment Capabilities Register (CLIST1_PMC)
PCI Power Management Control Status & Data Register (PMCS_DR)
Capabilities List 2 & Message Control Register (CLIST2_MCTL)
Message Address Low Register (MADDL)
Message Address High Register (MADDH)
Message Data Register (MDAT)
GbE Memory Mapped I/O
Gigabit Ethernet Capabilities and Status (GBECSR_00)
Gigabit Ethernet Capabilities and Status (GBECSR_18)
Gigabit Ethernet Capabilities and Status (GBECSR_20)
Gigabit Ethernet Capabilities and Status (GBECSR_F00)
Gigabit Ethernet Capabilities and Status F10 (GBECSR_F10)
Gigabit Ethernet Capabilities and Status (GBECSR_5400)
Gigabit Ethernet Capabilities and Status (GBECSR_5404)
Gigabit Ethernet Capabilities and Status (GBECSR_5800)
Gigabit Ethernet Capabilities and Status (GBECSR_5B54)
Generic SPI (GSPI) Additional
CLOCKS (CLOCKS)
RESETS (RESETS)
ACTIVE LTR (ACTIVELTR_VALUE)
Idle LTR Value (IDLELTR_VALUE)
TX Bit Count (TX_BIT_COUNT)
Rx Bit Count (RX_BIT_COUNT)
DMA Finish Disable (SSP_REG)
SPI CS CONTROL (SPI_CS_CONTROL)
reg_SW_Scratch_0 (SW_SCRATCH)
Clock Gate (CLOCK_GATE)
Remap Address Low (REMAP_ADDR_LO)
Remap Address High (REMAP_ADDR_HI)
Device Idle Control (DEVIDLE_CONTROL)
Delay Rx Clock (DEL_RX_CLK)
Capabilities (CAPABLITIES)
Generic SPI (GSPI) DMA Controller
CH 1 Linked List Pointer Low (LLP_LO1)
CH 1 Linked List Pointer High (LLP_HI1)
Raw Interrupt Status (RawTfr)
DMA Transfer Source Address Low (SAR_LO0)
DMA Transfer Source Address High (SAR_HI0)
DMA Transfer Destination Address Low (DAR_LO0)
DMA Transfer Destination Address High (DAR_HI0)
CH 0 Linked List Pointer Low (LLP_LO0)
CH 0 Linked List Pointer High (LLP_HI0)
Raw Status for Block Interrupts (RawBlock)
Raw Status for Source Transaction Interrupts (RawSrcTran)
Raw Status for Destination Transaction Interrupts (RawDstTran)
Control Register Low (CTL_LO0)
Control Register High (CTL_HI0)
Source Status (SSTAT0)
Destination Status (DSTAT0)
Source Status Address Low (SSTATAR_LO0)
Source Status Address High (SSTATAR_HI0)
Destination Status Address Low (DSTATAR_LO0)
Destination Status Address High (DSTATAR_HI0)
DMA Transfer Configuration Low (CFG_LO0)
DMA Transfer Configuration High (CFG_HI0)
Source Gather (SGR0)
Destination Scatter (DSR0)
Raw Status for Error Interrupts (RawErr)
Interrupt Status (StatusTfr)
Status for Block Interrupts (StatusBlock)
Status for Source Transaction Interrupts (StatusSrcTran)
Status for Destination Transaction Interrupts (StatusDstTran)
Status for Error Interrupts (StatusErr)
Mask for Transfer Interrupts (MaskTfr)
Mask for Block Interrupts (MaskBlock)
Mask for Source Transaction Interrupts (MaskSrcTran)
Mask for Destination Transaction Interrupts (MaskDstTran)
Mask for Error Interrupts (MaskErr)
Clear for Transfer Interrupts (ClearTfr)
Clear for Block Interrupts (ClearBlock)
Clear for Source Transaction Interrupts (ClearSrcTran)
Clear for Destination Transaction Interrupts (ClearDstTran)
Clear for Error Interrupts (ClearErr)
Combined Status register (StatusInt)
DMA Configuration (DmaCfgReg)
DMA Channel Enable (ChEnReg)
GPIO Community 0
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_A_0)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_A_0)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_A_1)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_A_1)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_A_2)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_A_2)
Family Base Address (FAMBAR)
Pad Base Address (PADBAR)
Miscellaneous Configuration (MISCCFG)
Pad Ownership (PAD_OWN_GPP_A_0)
Pad Ownership (PAD_OWN_GPP_A_1)
Pad Ownership (PAD_OWN_GPP_A_2)
Pad Ownership (PAD_OWN_GPP_B_0)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_A_3)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_A_3)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_A_4)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_A_4)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_A_5)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_A_5)
Pad Ownership (PAD_OWN_GPP_B_1)
Pad Ownership (PAD_OWN_GPP_B_2)
Pad Ownership (PAD_OWN_GPP_G_0)
Pad Configuration Lock (PADCFGLOCK_GPP_A_0)
Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_A_0)
Pad Configuration Lock (PADCFGLOCK_GPP_B_0)
Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_B_0)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_A_6)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_A_6)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_A_7)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_A_7)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_A_8)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_A_8)
Pad Configuration Lock (PADCFGLOCK_GPP_G_0)
Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_G_0)
Host Software Pad Ownership (HOSTSW_OWN_GPP_A_0)
Host Software Pad Ownership (HOSTSW_OWN_GPP_B_0)
Host Software Pad Ownership (HOSTSW_OWN_GPP_G_0)
GPI Interrupt Status (GPI_IS_GPP_A_0)
GPI Interrupt Status (GPI_IS_GPP_B_0)
GPI Interrupt Status (GPI_IS_GPP_G_0)
GPI Interrupt Enable (GPI_IE_GPP_A_0)
GPI Interrupt Enable (GPI_IE_GPP_B_0)
GPI Interrupt Enable (GPI_IE_GPP_G_0)
GPI General Purpose Events Status (GPI_GPE_STS_GPP_A_0)
GPI General Purpose Events Status (GPI_GPE_STS_GPP_B_0)
GPI General Purpose Events Status (GPI_GPE_STS_GPP_G_0)
GPI General Purpose Events Enable (GPI_GPE_EN_GPP_A_0)
GPI General Purpose Events Enable (GPI_GPE_EN_GPP_B_0)
GPI General Purpose Events Enable (GPI_GPE_EN_GPP_G_0)
SMI Status (GPI_SMI_STS_GPP_B_0)
SMI Enable (GPI_SMI_EN_GPP_B_0)
NMI Status (GPI_NMI_STS_GPP_B_0)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_A_9)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_A_9)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_A_10)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_A_10)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_A_11)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_A_11)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_A_12)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_A_12)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_A_13)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_A_13)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_A_14)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_A_14)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_A_15)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_A_15)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_A_16)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_A_16)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_A_17)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_A_17)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_A_18)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_A_18)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_A_19)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_A_19)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_A_20)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_A_20)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_A_21)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_A_21)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_A_22)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_A_22)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_A_23)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_A_23)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_B_0)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_B_0)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_B_1)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_B_1)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_B_2)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_B_2)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_B_3)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_B_3)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_B_4)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_B_4)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_B_5)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_B_5)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_B_6)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_B_6)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_B_7)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_B_7)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_B_8)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_B_8)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_B_9)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_B_9)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_B_10)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_B_10)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_B_11)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_B_11)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_B_12)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_B_12)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_B_13)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_B_13)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_B_14)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_B_14)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_B_15)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_B_15)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_B_16)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_B_16)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_B_17)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_B_17)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_B_18)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_B_18)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_B_19)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_B_19)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_B_20)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_B_20)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_B_21)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_B_21)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_B_22)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_B_22)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_B_23)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_B_23)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_G_0)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_G_0)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_G_1)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_G_1)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_G_2)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_G_2)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_G_3)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_G_3)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_G_4)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_G_4)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_G_5)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_G_5)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_G_6)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_G_6)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_G_7)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_G_7)
NMI Enable (GPI_NMI_EN_GPP_B_0)
GPIO Community 1
SMI Status (GPI_SMI_STS_GPP_D_0)
SMI Enable (GPI_SMI_EN_GPP_D_0)
NMI Status (GPI_NMI_STS_GPP_D_0)
NMI Enable (GPI_NMI_EN_GPP_D_0)
PWM Control (PWMC)
GPIO Serial Blink Enable (GP_SER_BLINK)
Family Base Address (FAMBAR)
Pad Base Address (PADBAR)
Miscellaneous Configuration (MISCCFG)
Pad Ownership (PAD_OWN_GPP_D_0)
Pad Ownership (PAD_OWN_GPP_D_1)
Pad Ownership (PAD_OWN_GPP_D_2)
Pad Ownership (PAD_OWN_GPP_F_0)
Pad Ownership (PAD_OWN_GPP_F_1)
Pad Ownership (PAD_OWN_GPP_F_2)
Pad Ownership (PAD_OWN_GPP_H_0)
Pad Ownership (PAD_OWN_GPP_H_1)
Pad Ownership (PAD_OWN_GPP_H_2)
Pad Configuration Lock (PADCFGLOCK_GPP_D_0)
Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_D_0)
GPIO Serial Blink Command/Status (GP_SER_CMDSTS)
GPIO Serial Blink Data (GP_SER_DATA)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_D_0)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_D_0)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_D_1)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_D_1)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_D_2)
Pad Configuration Lock (PADCFGLOCK_GPP_F_0)
Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_F_0)
Pad Configuration Lock (PADCFGLOCK_GPP_H_0)
Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_H_0)
Host Software Pad Ownership (HOSTSW_OWN_GPP_D_0)
Host Software Pad Ownership (HOSTSW_OWN_GPP_F_0)
Host Software Pad Ownership (HOSTSW_OWN_GPP_H_0)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_D_2)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_D_3)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_D_3)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_D_4)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_D_4)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_D_5)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_D_5)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_D_6)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_D_6)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_D_7)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_D_7)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_D_8)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_D_8)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_D_9)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_D_9)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_D_10)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_D_10)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_D_11)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_D_11)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_D_12)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_D_12)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_D_13)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_D_13)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_D_14)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_D_14)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_D_15)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_D_15)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_D_16)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_D_16)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_D_17)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_D_17)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_D_18)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_D_18)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_D_19)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_D_19)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_D_20)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_D_20)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_D_21)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_D_21)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_D_22)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_D_22)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_D_23)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_D_23)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_0)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_0)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_1)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_1)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_2)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_2)
Host Software Pad Ownership (HOSTSW_OWN_vGPIO_1)
GPI Interrupt Status (GPI_IS_GPP_D_0)
GPI Interrupt Status (GPI_IS_GPP_F_0)
GPI Interrupt Status (GPI_IS_GPP_H_0)
GPI Interrupt Status (GPI_IS_vGPIO_1)
GPI Interrupt Enable (GPI_IE_GPP_D_0)
GPI Interrupt Enable (GPI_IE_GPP_F_0)
GPI Interrupt Enable (GPI_IE_GPP_H_0)
GPI Interrupt Enable (GPI_IE_vGPIO_1)
GPI General Purpose Events Status (GPI_GPE_STS_GPP_D_0)
GPI General Purpose Events Status (GPI_GPE_STS_GPP_F_0)
GPI General Purpose Events Status (GPI_GPE_STS_GPP_H_0)
GPI General Purpose Events Status (GPI_GPE_STS_vGPIO_1)
GPI General Purpose Events Enable (GPI_GPE_EN_GPP_D_0)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_3)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_3)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_4)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_4)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_5)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_5)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_6)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_6)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_7)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_7)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_8)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_8)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_9)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_9)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_10)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_10)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_11)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_11)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_12)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_12)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_13)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_13)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_14)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_14)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_15)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_15)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_16)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_16)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_17)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_17)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_18)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_18)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_19)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_19)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_20)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_20)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_21)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_21)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_22)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_22)
Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_23)
Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_23)
GPI General Purpose Events Enable (GPI_GPE_EN_GPP_F_0)
GPI General Purpose Events Enable (GPI_GPE_EN_GPP_H_0)
GPI General Purpose Events Enable (GPI_GPE_EN_vGPIO_1)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_H_3)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_H_3)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_H_4)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_H_4)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_H_5)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_H_5)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_H_6)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_H_6)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_H_7)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_H_7)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_H_8)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_H_8)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_H_9)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_H_9)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_H_10)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_H_10)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_H_11)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_H_11)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_H_12)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_H_12)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_H_13)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_H_13)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_H_14)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_H_14)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_H_15)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_H_15)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_H_16)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_H_16)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_H_17)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_H_17)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_H_18)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_H_18)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_H_19)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_H_19)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_H_20)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_H_20)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_H_21)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_H_21)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_H_22)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_H_22)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_H_23)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_H_23)
Pad Configuration DW0 (PAD_CFG_DW0_vGPIO_0)
Pad Configuration DW0 (PAD_CFG_DW0_vGPIO_3)
Pad Configuration DW0 (PAD_CFG_DW0_vGPIO_30)
Pad Configuration DW0 (PAD_CFG_DW0_vGPIO_31)
Pad Configuration DW0 (PAD_CFG_DW0_vGPIO_32)
Pad Configuration DW0 (PAD_CFG_DW0_vGPIO_33)
Pad Configuration DW0 (PAD_CFG_DW0_vGPIO_34)
Pad Configuration DW0 (PAD_CFG_DW0_vGPIO_35)
Pad Configuration DW0 (PAD_CFG_DW0_vGPIO_36)
Pad Configuration DW0 (PAD_CFG_DW0_vGPIO_37)
Pad Configuration DW0 (PAD_CFG_DW0_vGPIO_39)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_H_0)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_H_0)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_H_1)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_H_1)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_H_2)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_H_2)
GPIO Community 2
Family Base Address (FAMBAR)
Pad Base Address (PADBAR)
Miscellaneous Configuration (MISCCFG)
Pad Ownership (PAD_OWN_DSW_0)
Pad Ownership (PAD_OWN_DSW_1)
Pad Configuration Lock (PADCFGLOCK_DSW_0)
Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_DSW_0)
Pad Configuration DW0 (PAD_CFG_DW0_GPD_0)
Pad Configuration DW1 (PAD_CFG_DW1_GPD_0)
Pad Configuration DW0 (PAD_CFG_DW0_GPD_1)
Pad Configuration DW1 (PAD_CFG_DW1_GPD_1)
Pad Configuration DW0 (PAD_CFG_DW0_GPD_2)
Pad Configuration DW1 (PAD_CFG_DW1_GPD_2)
Pad Configuration DW0 (PAD_CFG_DW0_GPD_3)
Pad Configuration DW1 (PAD_CFG_DW1_GPD_3)
Pad Configuration DW2 (PAD_CFG_DW2_GPD_3)
Pad Configuration DW0 (PAD_CFG_DW0_GPD_4)
Pad Configuration DW1 (PAD_CFG_DW1_GPD_4)
Pad Configuration DW0 (PAD_CFG_DW0_GPD_5)
Pad Configuration DW1 (PAD_CFG_DW1_GPD_5)
Pad Configuration DW0 (PAD_CFG_DW0_GPD_6)
Pad Configuration DW1 (PAD_CFG_DW1_GPD_6)
Pad Configuration DW0 (PAD_CFG_DW0_GPD_7)
Pad Configuration DW1 (PAD_CFG_DW1_GPD_7)
Pad Configuration DW0 (PAD_CFG_DW0_GPD_8)
Pad Configuration DW1 (PAD_CFG_DW1_GPD_8)
Pad Configuration DW0 (PAD_CFG_DW0_GPD_9)
Pad Configuration DW1 (PAD_CFG_DW1_GPD_9)
Host Software Pad Ownership (HOSTSW_OWN_DSW_0)
GPI Interrupt Enable (GPI_IE_DSW_0)
GPI General Purpose Events Status (GPI_GPE_STS_DSW_0)
GPI General Purpose Events Enable (GPI_GPE_EN_DSW_0)
Pad Configuration DW0 (PAD_CFG_DW0_GPD_10)
Pad Configuration DW1 (PAD_CFG_DW1_GPD_10)
Pad Configuration DW0 (PAD_CFG_DW0_GPD_11)
Pad Configuration DW1 (PAD_CFG_DW1_GPD_11)
GPIO Community 3
Pad Configuration DW0 (PAD_CFG_DW0_HDA_BCLK)
Pad Configuration DW0 (PAD_CFG_DW0_HDA_RSTB)
Pad Configuration DW0 (PAD_CFG_DW0_HDA_SYNC)
Pad Configuration DW0 (PAD_CFG_DW0_HDA_SDO)
Pad Configuration DW0 (PAD_CFG_DW0_HDA_SDI_0)
Pad Configuration DW0 (PAD_CFG_DW0_HDA_SDI_1)
Pad Configuration DW0 (PAD_CFG_DW0_SSP1_SFRM)
Pad Configuration DW0 (PAD_CFG_DW0_SSP1_TXD)
GPIO Community 4
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_C_18)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_C_18)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_C_19)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_C_19)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_C_20)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_C_20)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_C_21)
Family Base Address (FAMBAR)
Pad Base Address (PADBAR)
Miscellaneous Configuration (MISCCFG)
Pad Ownership (PAD_OWN_GPP_C_0)
Pad Ownership (PAD_OWN_GPP_C_1)
Pad Ownership (PAD_OWN_GPP_C_2)
Pad Ownership (PAD_OWN_GPP_E_0)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_C_21)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_C_22)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_C_22)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_C_23)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_C_23)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_E_0)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_E_0)
Pad Ownership (PAD_OWN_GPP_E_1)
Pad Ownership (PAD_OWN_GPP_E_2)
Pad Configuration Lock (PADCFGLOCK_GPP_C_0)
Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_C_0)
Pad Configuration Lock (PADCFGLOCK_GPP_E_0)
Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_E_0)
Host Software Pad Ownership (HOSTSW_OWN_GPP_C_0)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_E_1)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_E_1)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_E_2)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_E_2)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_E_3)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_E_3)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_E_4)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_E_4)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_E_5)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_E_5)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_E_6)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_E_6)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_E_7)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_E_7)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_E_8)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_E_8)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_E_9)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_E_9)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_E_10)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_E_10)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_E_11)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_E_11)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_E_12)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_E_12)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_E_13)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_E_13)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_E_14)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_E_14)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_E_15)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_E_15)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_E_16)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_E_16)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_E_17)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_E_17)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_E_18)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_E_18)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_E_19)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_E_19)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_E_20)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_E_20)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_E_21)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_E_21)
Host Software Pad Ownership (HOSTSW_OWN_GPP_E_0)
GPI Interrupt Status (GPI_IS_GPP_C_0)
GPI Interrupt Status (GPI_IS_GPP_E_0)
GPI Interrupt Enable (GPI_IE_GPP_C_0)
GPI Interrupt Enable (GPI_IE_GPP_E_0)
GPI General Purpose Events Status (GPI_GPE_STS_GPP_C_0)
GPI General Purpose Events Status (GPI_GPE_STS_GPP_E_0)
GPI General Purpose Events Enable (GPI_GPE_EN_GPP_C_0)
GPI General Purpose Events Enable (GPI_GPE_EN_GPP_E_0)
SMI Status (GPI_SMI_STS_GPP_C_0)
SMI Status (GPI_SMI_STS_GPP_E_0)
NMI Status (GPI_NMI_STS_GPP_C_0)
NMI Status (GPI_NMI_STS_GPP_E_0)
NMI Enable (GPI_NMI_EN_GPP_C_0)
NMI Enable (GPI_NMI_EN_GPP_E_0)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_C_0)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_C_0)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_C_1)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_C_1)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_C_2)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_C_2)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_C_3)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_C_3)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_C_4)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_C_4)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_C_5)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_C_5)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_C_6)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_C_6)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_C_7)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_C_7)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_C_8)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_C_8)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_C_9)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_C_9)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_C_10)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_C_10)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_C_11)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_C_11)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_C_12)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_C_12)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_C_13)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_C_13)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_C_14)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_C_14)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_C_15)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_C_15)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_C_16)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_C_16)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_E_22)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_E_22)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_E_23)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_E_23)
Pad Configuration DW0 (PAD_CFG_DW0_GPPC_C_17)
Pad Configuration DW1 (PAD_CFG_DW1_GPPC_C_17)
GSPI PCI Configuration
Device ID and Vendor ID (DEVVENDID)
Status and Command (STATUSCOMMAND)
Revision ID and Class Code (REVCLASSCODE)
Cache Line Latency Header and BIST (CLLATHEADERBIST)
Base Address (BAR)
Base Address High (BAR_HIGH)
Base Address 1 (BAR1)
Base Address 1 High (BAR1_HIGH)
Subsystem Vendor and Subsystem ID (SUBSYSTEMID)
Capabilities Pointer (CAPABILITYPTR)
Interrupt (INTERRUPTREG)
Power Management Capability ID (POWERCAPID)
Power Management Control and Status (PMECTRLSTATUS)
PCI Device Idle Capability Record (PCIDEVIDLE_CAP_RECORD)
SW LTR Update MMIO Location (D0I3_CONTROL_SW_LTR_MMIO_REG)
Device IDLE Pointer (DEVICE_IDLE_POINTER_REG)
Device PG Config (D0I3_MAX_POW_LAT_PG_CONFIG)
General Purpose Read Write 1 (GEN_REGRW1)
General Purpose Read Write 2 (GEN_REGRW2)
General Purpose Read Write 3 (GEN_REGRW3)
General Purpose Read Write 4 (GEN_REGRW4)
General Purpose Input (GEN_INPUT_REG)
High Definition Audio (D31:F3) Memory Mapped I/O
Global Capabilities (GCAP)
Minor Version (VMIN)
Major Version (VMAJ)
Output Payload Capability (OUTPAY)
Input Payload Capability (INPAY)
Global Control (GCTL)
Wake Enable (WAKEEN)
Processing Pipe Capability Header (PPCH)
Processing Pipe Control (PPCTL)
Processing Pipe Status (PPSTS)
Input/Output Processing Pipe's Host Connection x Linear Link Position Lower (IPPHC0LLPL)
Input/Output Processing Pipe's Host Connection x Linear Link Position Upper (IPPHC0LLPU)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower (IPPHC0LDPL)
Wake Status (WAKESTS)
Global Status (GSTS)
Global Capabilities 2 (GCAP2)
Linked List Capabilities Header (LLCH)
Output Stream Payload Capability (OUTSTRMPAY)
Input Stream Payload Capability (INSTRMPAY)
Interrupt Control (INTCTL)
Interrupt Status (INTSTS)
Wall Clock Counter (WALCLK)
Stream Synchronization (SSYNC)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper (IPPHC0LDPU)
Input/Output Processing Pipe's Host Connection x Linear Link Position Lower (IPPHC1LLPL)
Input/Output Processing Pipe's Host Connection x Linear Link Position Upper (IPPHC1LLPU)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower (IPPHC1LDPL)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper (IPPHC1LDPU)
Input/Output Processing Pipe's Host Connection x Linear Link Position Lower (IPPHC2LLPL)
Input/Output Processing Pipe's Host Connection x Linear Link Position Upper (IPPHC2LLPU)
CORB Lower Base Address (CORBLBASE)
CORB Upper Base Address (CORBUBASE)
CORB Write Pointer (CORBWP)
CORB Read Pointer (CORBRP)
CORB Control (CORBCTL)
CORB Status (CORBSTS)
CORB Size (CORBSIZE)
RIRB Lower Base Address (RIRBLBASE)
RIRB Upper Base Address (RIRBUBASE)
RIRB Write Pointer (RIRBWP)
Response Interrupt Count (RINTCNT)
RIRB Control (RIRBCTL)
RIRB Status (RIRBSTS)
RIRB Size (RIRBSIZE)
Immediate Command (IC)
Immediate Response (IR)
Immediate Command Status (ICS)
DMA Position Lower Base Address (DPLBASE)
DMA Position Upper Base Address (DPUBASE)
Input/Output Stream Descriptor x Control (ISD0CTL)
Input/Output Stream Descriptor x Status (ISD0STS)
Input/Output Stream Descriptor x Link Position in Buffer (ISD0LPIB)
Input/Output Stream Descriptor x Cyclic Buffer Length (ISD0CBL)
Input/Output Stream Descriptor x Last Valid Index (ISD0LVI)
Input/Output Stream Descriptor x FIFO Eviction Watermark (ISD0FIFOW)
Input/Output Stream Descriptor x FIFO Size (ISD0FIFOS)
Input/Output Stream Descriptor x Format (ISD0FMT)
Input/Output Stream Descriptor x FIFO Limit (ISD0FIFOL)
Input/Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD0BDLPLBA)
Input/Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD0BDLPUBA)
Input/Output Processing Pipe's Host Connection x Linear Link Position Upper (OPPHC8LLPU)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower (OPPHC8LDPL)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper (OPPHC8LDPU)
Input/Output Processing Pipe's Link Connection x Control (IPPLC0CTL)
Input/Output Processing Pipe's Link Connection x Format (IPPLC0FMT)
Input/Output Processing Pipe's Link Connection x Linear Link Position Lower (IPPLC0LLPL)
Input/Output Processing Pipe's Link Connection x Linear Link Position Upper (IPPLC0LLPU)
Input/Output Processing Pipe's Link Connection x Control (IPPLC1CTL)
Input/Output Processing Pipe's Link Connection x Format (IPPLC1FMT)
Input/Output Processing Pipe's Link Connection x Linear Link Position Lower (IPPLC1LLPL)
Input/Output Processing Pipe's Link Connection x Linear Link Position Upper (IPPLC1LLPU)
Input/Output Processing Pipe's Link Connection x Control (IPPLC2CTL)
Input/Output Processing Pipe's Link Connection x Format (IPPLC2FMT)
Input/Output Processing Pipe's Link Connection x Linear Link Position Lower (IPPLC2LLPL)
Input/Output Processing Pipe's Link Connection x Linear Link Position Upper (IPPLC2LLPU)
Input/Output Processing Pipe's Link Connection x Control (IPPLC3CTL)
Input/Output Processing Pipe's Link Connection x Format (IPPLC3FMT)
Input/Output Processing Pipe's Link Connection x Linear Link Position Lower (IPPLC3LLPL)
Input/Output Processing Pipe's Link Connection x Linear Link Position Upper (IPPLC3LLPU)
Input/Output Processing Pipe's Link Connection x Control (IPPLC4CTL)
Input/Output Processing Pipe's Link Connection x Format (IPPLC4FMT)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower (IPPHC2LDPL)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper (IPPHC2LDPU)
Input/Output Processing Pipe's Host Connection x Linear Link Position Lower (IPPHC3LLPL)
Input/Output Processing Pipe's Host Connection x Linear Link Position Upper (IPPHC3LLPU)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower (IPPHC3LDPL)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper (IPPHC3LDPU)
Input/Output Processing Pipe's Host Connection x Linear Link Position Lower (IPPHC4LLPL)
Input/Output Processing Pipe's Link Connection x Linear Link Position Lower (IPPLC4LLPL)
Input/Output Processing Pipe's Link Connection x Linear Link Position Upper (IPPLC4LLPU)
Input/Output Processing Pipe's Link Connection x Control (IPPLC5CTL)
Input/Output Processing Pipe's Link Connection x Format (IPPLC5FMT)
Input/Output Processing Pipe's Link Connection x Linear Link Position Lower (IPPLC5LLPL)
Input/Output Processing Pipe's Link Connection x Linear Link Position Upper (IPPLC5LLPU)
Input/Output Processing Pipe's Link Connection x Control (IPPLC6CTL)
Input/Output Processing Pipe's Host Connection x Linear Link Position Upper (IPPHC4LLPU)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower (IPPHC4LDPL)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper (IPPHC4LDPU)
Input/Output Processing Pipe's Host Connection x Linear Link Position Lower (IPPHC5LLPL)
Input/Output Processing Pipe's Host Connection x Linear Link Position Upper (IPPHC5LLPU)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower (IPPHC5LDPL)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper (IPPHC5LDPU)
Input/Output Processing Pipe's Link Connection x Format (IPPLC6FMT)
Input/Output Processing Pipe's Link Connection x Linear Link Position Lower (IPPLC6LLPL)
Input/Output Processing Pipe's Link Connection x Linear Link Position Upper (IPPLC6LLPU)
Input/Output Processing Pipe's Link Connection x Control (OPPLC0CTL)
Input/Output Processing Pipe's Link Connection x Format (OPPLC0FMT)
Input/Output Processing Pipe's Link Connection x Linear Link Position Lower (OPPLC0LLPL)
Input/Output Processing Pipe's Link Connection x Linear Link Position Upper (OPPLC0LLPU)
Input/Output Processing Pipe's Link Connection x Control (OPPLC1CTL)
Input/Output Processing Pipe's Link Connection x Format (OPPLC1FMT)
Input/Output Processing Pipe's Link Connection x Linear Link Position Lower (OPPLC1LLPL)
Input/Output Processing Pipe's Link Connection x Linear Link Position Upper (OPPLC1LLPU)
Input/Output Processing Pipe's Link Connection x Control (OPPLC2CTL)
Input/Output Processing Pipe's Link Connection x Format (OPPLC2FMT)
Input/Output Processing Pipe's Link Connection x Linear Link Position Lower (OPPLC2LLPL)
Input/Output Processing Pipe's Link Connection x Linear Link Position Upper (OPPLC2LLPU)
Input/Output Processing Pipe's Link Connection x Control (OPPLC3CTL)
Input/Output Processing Pipe's Link Connection x Format (OPPLC3FMT)
Input/Output Processing Pipe's Link Connection x Linear Link Position Lower (OPPLC3LLPL)
Input/Output Processing Pipe's Link Connection x Linear Link Position Upper (OPPLC3LLPU)
Input/Output Processing Pipe's Link Connection x Control (OPPLC4CTL)
Input/Output Processing Pipe's Link Connection x Format (OPPLC4FMT)
Input/Output Processing Pipe's Link Connection x Linear Link Position Lower (OPPLC4LLPL)
Input/Output Processing Pipe's Link Connection x Linear Link Position Upper (OPPLC4LLPU)
Input/Output Processing Pipe's Link Connection x Control (OPPLC5CTL)
Input/Output Processing Pipe's Link Connection x Format (OPPLC5FMT)
Input/Output Processing Pipe's Link Connection x Linear Link Position Lower (OPPLC5LLPL)
Input/Output Processing Pipe's Link Connection x Linear Link Position Upper (OPPLC5LLPU)
Input/Output Processing Pipe's Link Connection x Control (OPPLC6CTL)
Input/Output Processing Pipe's Link Connection x Format (OPPLC6FMT)
Input/Output Processing Pipe's Link Connection x Linear Link Position Lower (OPPLC6LLPL)
Input/Output Processing Pipe's Link Connection x Linear Link Position Upper (OPPLC6LLPU)
Input/Output Processing Pipe's Link Connection x Control (OPPLC7CTL)
Input/Output Processing Pipe's Link Connection x Format (OPPLC7FMT)
Input/Output Processing Pipe's Link Connection x Linear Link Position Lower (OPPLC7LLPL)
Input/Output Processing Pipe's Link Connection x Linear Link Position Upper (OPPLC7LLPU)
Input/Output Processing Pipe's Link Connection x Control (OPPLC8CTL)
Input/Output Processing Pipe's Link Connection x Format (OPPLC8FMT)
Input/Output Processing Pipe's Link Connection x Linear Link Position Lower (OPPLC8LLPL)
Input/Output Processing Pipe's Link Connection x Linear Link Position Upper (OPPLC8LLPU)
Input/Output Processing Pipe's Host Connection x Linear Link Position Lower (IPPHC7LLPL)
Input/Output Processing Pipe's Host Connection x Linear Link Position Upper (IPPHC7LLPU)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower (IPPHC7LDPL)
Input/Output Processing Pipe's Host Connection x Linear Link Position Lower (IPPHC6LLPL)
Input/Output Processing Pipe's Host Connection x Linear Link Position Upper (IPPHC6LLPU)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower (IPPHC6LDPL)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper (IPPHC6LDPU)
Input/Output Processing Pipe's Host Connection x Linear Link Position Lower (OPPHC0LLPL)
Input/Output Processing Pipe's Host Connection x Linear Link Position Upper (OPPHC0LLPU)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower (OPPHC0LDPL)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper (IPPHC7LDPU)
Input/Output Processing Pipe's Host Connection x Linear Link Position Lower (IPPHC8LLPL)
Input/Output Processing Pipe's Host Connection x Linear Link Position Upper (IPPHC8LLPU)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower (IPPHC8LDPL)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper (IPPHC8LDPU)
Input/Output Processing Pipe's Host Connection x Linear Link Position Lower (IPPHC9LLPL)
Input/Output Processing Pipe's Host Connection x Linear Link Position Upper (IPPHC9LLPU)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper (OPPHC0LDPU)
Input/Output Processing Pipe's Host Connection x Linear Link Position Lower (OPPHC1LLPL)
Input/Output Processing Pipe's Host Connection x Linear Link Position Upper (OPPHC1LLPU)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower (OPPHC1LDPL)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper (OPPHC1LDPU)
Input/Output Processing Pipe's Host Connection x Linear Link Position Lower (OPPHC2LLPL)
Input/Output Processing Pipe's Host Connection x Linear Link Position Upper (OPPHC2LLPU)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower (IPPHC9LDPL)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper (IPPHC9LDPU)
Input/Output Processing Pipe's Host Connection x Linear Link Position Lower (IPPHC10LLPL)
Input/Output Processing Pipe's Host Connection x Linear Link Position Upper (IPPHC10LLPU)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower (IPPHC10LDPL)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper (IPPHC10LDPU)
Input/Output Processing Pipe's Host Connection x Linear Link Position Lower (IPPHC11LLPL)
Input/Output Processing Pipe's Host Connection x Linear Link Position Upper (IPPHC11LLPU)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower (IPPHC11LDPL)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper (IPPHC11LDPU)
Input/Output Processing Pipe's Host Connection x Linear Link Position Lower (IPPHC12LLPL)
Input/Output Processing Pipe's Host Connection x Linear Link Position Upper (IPPHC12LLPU)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower (IPPHC12LDPL)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper (IPPHC12LDPU)
Input/Output Processing Pipe's Host Connection x Linear Link Position Lower (IPPHC13LLPL)
Input/Output Processing Pipe's Host Connection x Linear Link Position Upper (IPPHC13LLPU)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower (IPPHC13LDPL)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper (IPPHC13LDPU)
Input/Output Processing Pipe's Host Connection x Linear Link Position Lower (IPPHC14LLPL)
Input/Output Processing Pipe's Host Connection x Linear Link Position Upper (IPPHC14LLPU)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower (IPPHC14LDPL)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper (IPPHC14LDPU)
Input/Output Processing Pipe's Host Connection x Linear Link Position Lower (OPPHC9LLPL)
Input/Output Processing Pipe's Host Connection x Linear Link Position Upper (OPPHC9LLPU)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower (OPPHC9LDPL)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper (OPPHC9LDPU)
Input/Output Processing Pipe's Host Connection x Linear Link Position Lower (OPPHC10LLPL)
Input/Output Processing Pipe's Host Connection x Linear Link Position Upper (OPPHC10LLPU)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower (OPPHC10LDPL)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper (OPPHC10LDPU)
Input/Output Processing Pipe's Host Connection x Linear Link Position Lower (OPPHC11LLPL)
Input/Output Processing Pipe's Host Connection x Linear Link Position Upper (OPPHC11LLPU)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower (OPPHC11LDPL)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper (OPPHC11LDPU)
Input/Output Processing Pipe's Host Connection x Linear Link Position Lower (OPPHC12LLPL)
Input/Output Processing Pipe's Host Connection x Linear Link Position Upper (OPPHC12LLPU)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower (OPPHC12LDPL)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper (OPPHC12LDPU)
Input/Output Processing Pipe's Host Connection x Linear Link Position Lower (OPPHC13LLPL)
Input/Output Processing Pipe's Host Connection x Linear Link Position Upper (OPPHC13LLPU)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower (OPPHC13LDPL)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper (OPPHC13LDPU)
Input/Output Processing Pipe's Host Connection x Linear Link Position Lower (OPPHC14LLPL)
Input/Output Processing Pipe's Host Connection x Linear Link Position Upper (OPPHC14LLPU)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower (OPPHC14LDPL)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper (OPPHC14LDPU)
Input/Output Processing Pipe's Link Connection x Control (IPPLC7CTL)
Input/Output Processing Pipe's Link Connection x Format (IPPLC7FMT)
Input/Output Processing Pipe's Link Connection x Linear Link Position Lower (IPPLC7LLPL)
Input/Output Processing Pipe's Link Connection x Linear Link Position Upper (IPPLC7LLPU)
Input/Output Processing Pipe's Link Connection x Control (IPPLC8CTL)
Input/Output Processing Pipe's Link Connection x Format (IPPLC8FMT)
Input/Output Processing Pipe's Link Connection x Linear Link Position Lower (IPPLC8LLPL)
Input/Output Processing Pipe's Link Connection x Linear Link Position Upper (IPPLC8LLPU)
Input/Output Processing Pipe's Link Connection x Control (IPPLC9CTL)
Input/Output Processing Pipe's Link Connection x Format (IPPLC9FMT)
Input/Output Processing Pipe's Link Connection x Linear Link Position Lower (IPPLC9LLPL)
Input/Output Processing Pipe's Link Connection x Linear Link Position Upper (IPPLC9LLPU)
Input/Output Processing Pipe's Link Connection x Control (IPPLC10CTL)
Input/Output Processing Pipe's Link Connection x Format (IPPLC10FMT)
Input/Output Processing Pipe's Link Connection x Linear Link Position Lower (IPPLC10LLPL)
Input/Output Processing Pipe's Link Connection x Linear Link Position Upper (IPPLC10LLPU)
Input/Output Processing Pipe's Link Connection x Control (IPPLC11CTL)
Input/Output Processing Pipe's Link Connection x Format (IPPLC11FMT)
Input/Output Processing Pipe's Link Connection x Linear Link Position Lower (IPPLC11LLPL)
Input/Output Processing Pipe's Link Connection x Linear Link Position Upper (IPPLC11LLPU)
Input/Output Processing Pipe's Link Connection x Control (IPPLC12CTL)
Input/Output Processing Pipe's Link Connection x Format (IPPLC12FMT)
Input/Output Processing Pipe's Link Connection x Linear Link Position Lower (IPPLC12LLPL)
Input/Output Processing Pipe's Link Connection x Linear Link Position Upper (IPPLC12LLPU)
Input/Output Processing Pipe's Link Connection x Control (IPPLC13CTL)
Input/Output Processing Pipe's Link Connection x Format (IPPLC13FMT)
Input/Output Processing Pipe's Link Connection x Linear Link Position Lower (IPPLC13LLPL)
Input/Output Processing Pipe's Link Connection x Linear Link Position Upper (IPPLC13LLPU)
Input/Output Processing Pipe's Link Connection x Control (IPPLC14CTL)
Input/Output Processing Pipe's Link Connection x Format (IPPLC14FMT)
Input/Output Processing Pipe's Link Connection x Linear Link Position Lower (IPPLC14LLPL)
Input/Output Processing Pipe's Link Connection x Linear Link Position Upper (IPPLC14LLPU)
Input/Output Processing Pipe's Link Connection x Control (OPPLC9CTL)
Input/Output Processing Pipe's Link Connection x Format (OPPLC9FMT)
Input/Output Processing Pipe's Link Connection x Linear Link Position Lower (OPPLC9LLPL)
Input/Output Processing Pipe's Link Connection x Linear Link Position Upper (OPPLC9LLPU)
Input/Output Processing Pipe's Link Connection x Control (OPPLC10CTL)
Input/Output Processing Pipe's Link Connection x Format (OPPLC10FMT)
Input/Output Processing Pipe's Link Connection x Linear Link Position Lower (OPPLC10LLPL)
Input/Output Processing Pipe's Link Connection x Linear Link Position Upper (OPPLC10LLPU)
Input/Output Processing Pipe's Link Connection x Control (OPPLC11CTL)
Input/Output Processing Pipe's Link Connection x Format (OPPLC11FMT)
Input/Output Processing Pipe's Link Connection x Linear Link Position Lower (OPPLC11LLPL)
Input/Output Processing Pipe's Link Connection x Linear Link Position Upper (OPPLC11LLPU)
Input/Output Processing Pipe's Link Connection x Control (OPPLC12CTL)
Input/Output Processing Pipe's Link Connection x Format (OPPLC12FMT)
Input/Output Processing Pipe's Link Connection x Linear Link Position Lower (OPPLC12LLPL)
Input/Output Processing Pipe's Link Connection x Linear Link Position Upper (OPPLC12LLPU)
Input/Output Processing Pipe's Link Connection x Control (OPPLC13CTL)
Input/Output Processing Pipe's Link Connection x Format (OPPLC13FMT)
Input/Output Processing Pipe's Link Connection x Linear Link Position Lower (OPPLC13LLPL)
Input/Output Processing Pipe's Link Connection x Linear Link Position Upper (OPPLC13LLPU)
Input/Output Processing Pipe's Link Connection x Control (OPPLC14CTL)
Input/Output Processing Pipe's Link Connection x Format (OPPLC14FMT)
Input/Output Processing Pipe's Link Connection x Linear Link Position Lower (OPPLC14LLPL)
Input/Output Processing Pipe's Link Connection x Linear Link Position Upper (OPPLC14LLPU)
Multiple Links Capability Header (MLCH)
Multiple Links Capability Declaration (MLCD)
Link x Capabilities (LCAP0)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower (OPPHC2LDPL)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper (OPPHC2LDPU)
Input/Output Processing Pipe's Host Connection x Linear Link Position Lower (OPPHC3LLPL)
Input/Output Processing Pipe's Host Connection x Linear Link Position Upper (OPPHC3LLPU)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower (OPPHC3LDPL)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper (OPPHC3LDPU)
Input/Output Processing Pipe's Host Connection x Linear Link Position Lower (OPPHC4LLPL)
Input/Output Processing Pipe's Host Connection x Linear Link Position Upper (OPPHC4LLPU)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower (OPPHC4LDPL)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper (OPPHC4LDPU)
Input/Output Processing Pipe's Host Connection x Linear Link Position Lower (OPPHC5LLPL)
Input/Output Processing Pipe's Host Connection x Linear Link Position Upper (OPPHC5LLPU)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower (OPPHC5LDPL)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper (OPPHC5LDPU)
Input/Output Processing Pipe's Host Connection x Linear Link Position Lower (OPPHC6LLPL)
Input/Output Processing Pipe's Host Connection x Linear Link Position Upper (OPPHC6LLPU)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower (OPPHC6LDPL)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper (OPPHC6LDPU)
Input/Output Processing Pipe's Host Connection x Linear Link Position Lower (OPPHC7LLPL)
Input/Output Processing Pipe's Host Connection x Linear Link Position Upper (OPPHC7LLPU)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower (OPPHC7LDPL)
Link 0 Control (LCTL0)
Link 1 Control (LCTL1)
Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper (OPPHC7LDPU)
Input/Output Processing Pipe's Host Connection x Linear Link Position Lower (OPPHC8LLPL)
High Definition Audio (D31:F3) PCI Configuration
Vendor Identification (VID)
Device ID (DID)
Command (CMD)
Status (STS)
Revision Identification (RID)
Programming Interface (PI)
Sub Class Code (SCC)
Base Class Code (BCC)
Cache Line Size (CLS)
Latency Timer (LT)
Header Type (HTYPE)
Intel HD Audio Base Lower Address (HDALBA)
Intel HD Audio Base Upper Address (HDAUBA)
Shadowed PCI Configuration Lower Base Address (SPCLBA)
Shadowed PCI Configuration Upper Base Address (SPCUBA)
Audio DSP Lower Base Address (ADSPLBA)
Audio DSP Upper Base Address (ADSPUBA)
Subsystem Vendor ID (SVID)
Subsystem ID (SID)
Capability Pointer (CAPPTR)
Interrupt Line (INTLN)
Interrupt Pin (INTPN)
Power Gating Control (PGCTL)
Clock Gating Control (CGCTL)
PCI Power Management Capability ID (PID)
Power Management Capabilities (PC)
Power Management Control And Status (PCS)
Message Signal Interrupt Message Control (MMC)
MSI Message Lower Address (MMLA)
MSI Message Upper Address (MMUA)
MSI Message Data (MMD)
PCI Express Capability ID (PXID)
PCI Express Capabilities (PXC)
Device Capabilities (DEVCAP)
Device Control (DEVC)
Device Status (DEVS)
I2C Additional
Soft Reset (RESETS)
Active LTR (ACTIVELTR_VALUE)
Idle LTR (IDLELTR_VALUE)
TX Ack Count (TX_ACK_COUNT)
RX ACK Count (RX_BYTE_COUNT)
Interrupt Status for Tx Complete (TX_COMPLETE_INTR_STAT)
Tx Complete Interrupt Clear (TX_COMPLETE_INTR_CLR)
SW Scratch Register 0 (SW_SCRATCH_0)
SW Scratch Register 1 (SW_SCRATCH_1)
SW Scratch Register 2 (SW_SCRATCH_2)
SW Scratch Register 3 (SW_SCRATCH_3)
Clock Gate (CLOCK_GATE)
Remap Address Low (REMAP_ADDR_LO)
Remap Address High (REMAP_ADDR_HI)
Device Control (DEVIDLE_CONTROL)
Capabilities (CAPABLITIES)
I2C DMA Controller
DMA Transfer Source Address Low (SAR_LO0)
DMA Transfer Source Address High (SAR_HI0)
DMA Transfer Destination Address Low (DAR_LO0)
Raw Status for Destination Transaction Interrupts (RawDstTran)
Raw Status for Error Interrupts (RawErr)
Interrupt Status (StatusTfr)
DMA Transfer Destination Address High (DAR_HI0)
CH 0 Linked List Pointer Low (LLP_LO0)
CH 0 Linked List Pointer High (LLP_HI0)
Status for Block Interrupts (StatusBlock)
Status for Source Transaction Interrupts (StatusSrcTran)
Status for Destination Transaction Interrupts (StatusDstTran)
Status for Error Interrupts (StatusErr)
Control Register Low (CTL_LO0)
Control Register High (CTL_HI0)
Source Status (SSTAT0)
Destination Status (DSTAT0)
Source Status Address Low (SSTATAR_LO0)
Source Status Address High (SSTATAR_HI0)
Destination Status Address Low (DSTATAR_LO0)
Destination Status Address High (DSTATAR_HI0)
DMA Transfer Configuration Low (CFG_LO0)
DMA Transfer Configuration High (CFG_HI0)
Source Gather (SGR0)
Destination Scatter (DSR0)
CH 1 Linked List Pointer Low (LLP_LO1)
CH 1 Linked List Pointer High (LLP_HI1)
Raw Interrupt Status (RawTfr)
Mask for Transfer Interrupts (MaskTfr)
Mask for Block Interrupts (MaskBlock)
Mask for Source Transaction Interrupts (MaskSrcTran)
Mask for Destination Transaction Interrupts (MaskDstTran)
Mask for Error Interrupts (MaskErr)
Clear for Transfer Interrupts (ClearTfr)
Clear for Block Interrupts (ClearBlock)
Clear for Source Transaction Interrupts (ClearSrcTran)
Clear for Destination Transaction Interrupts (ClearDstTran)
Clear for Error Interrupts (ClearErr)
Combined Status register (StatusInt)
Raw Status for Block Interrupts (RawBlock)
Raw Status for Source Transaction Interrupts (RawSrcTran)
DMA Configuration (DmaCfgReg)
DMA Channel Enable (ChEnReg)
I2C Memory Mapped
I2C Control (IC_CON)
I2C Target Address (IC_TAR)
I2C High Speed Master Mode Code Address (IC_HS_MADDR)
I2C Rx/Tx Data Buffer and Command (IC_DATA_CMD)
Standard Speed I2C Clock SCL High Count (IC_SS_SCL_HCNT)
Standard Speed I2C Clock SCL Low Count (IC_SS_SCL_LCNT)
Fast Speed I2C Clock SCL High Count (IC_FS_SCL_HCNT)
Fast Speed I2C Clock SCL Low Count (IC_FS_SCL_LCNT)
High Speed I2C Clock SCL High Count (IC_HS_SCL_HCNT)
High Speed I2C Clock SCL Low Count (IC_HS_SCL_LCNT)
I2C Interrupt Status (IC_INTR_STAT)
I2C Interrupt Mask (IC_INTR_MASK)
I2C Raw Interrupt Status (IC_RAW_INTR_STAT)
I2C Receive FIFO Threshold (IC_RX_TL)
I2C Transmit FIFO Threshold (IC_TX_TL)
Clear Combined and Individual Interrupt (IC_CLR_INTR)
Clear RX_UNDER Interrupt (IC_CLR_RX_UNDER)
Clear RX_OVER Interrupt (IC_CLR_RX_OVER)
Clear TX_OVER Interrupt (IC_CLR_TX_OVER)
Clear RD_REQ Interrupt (IC_CLR_RD_REQ)
Clear TX_ABRT Interrupt (IC_CLR_TX_ABRT)
Clear RX_DONE Interrupt (IC_CLR_RX_DONE)
Clear ACTIVITY Interrupt (IC_CLR_ACTIVITY)
Clear STOP_DET Interrupt (IC_CLR_STOP_DET)
Clear START_DET Interrupt (IC_CLR_START_DET)
Clear GEN_CALL Interrupt (IC_CLR_GEN_CALL)
I2C Enable (IC_ENABLE)
I2C Status (IC_STATUS)
I2C Transmit FIFO Level (IC_TXFLR)
I2C Receive FIFO Level (IC_RXFLR)
I2C SDA Hold Time Length (IC_SDA_HOLD)
I2C Transmit Abort Source (IC_TX_ABRT_SOURCE)
DMA Control (IC_DMA_CR)
DMA Transmit Data Level (IC_DMA_TDLR)
I2C Receive Data Level (IC_DMA_RDLR)
I2C ACK General Call (IC_ACK_GENERAL_CALL)
I2C Enable Status (IC_ENABLE_STATUS)
I2C SS and FS Spike Suppression Limit (IC_FS_SPKLEN)
Clear RESTART_DET Interrupt (IC_CLR_RESTRART_DET)
I2C PCI Congifuration
Device ID and Vendor ID (DEVVENDID)
Status and Command (STATUSCOMMAND)
Revision ID and Class Code (REVCLASSCODE)
Cache Line Latency Header and BIST (CLLATHEADERBIST)
Base Address (BAR)
Base Address Register High (BAR_HIGH)
Base Address 1 (BAR1)
Base Address 1 High (BAR1_HIGH)
Subsystem Vendor and Subsystem ID (SUBSYSTEMID)
Capabilities Pointer (CAPABILITYPTR)
Interrupt Register (INTERRUPTREG)
Power Management Capability ID (POWERCAPID)
Power Management Control and Status (PMECTRLSTATUS)
PCI Device Idle Capability Record (PCIDEVIDLE_CAP_RECORD)
SW LTR update MMIO Location (D0I3_CONTROL_SW_LTR_MMIO_REG)
Device IDLE Pointer (DEVICE_IDLE_POINTER_REG)
Device PG Config (D0I3_MAX_POW_LAT_PG_CONFIG)
General Purpose Read Write 1 (GEN_REGRW1)
General Purpose PCI Read Write 2 (GEN_REGRW2)
General Purpose PCI Read Write 3 (GEN_REGRW3)
General Purpose PCI Read Write 4 (GEN_REGRW4)
General Purpose Input (GEN_INPUT_REG)
IDE Redirect PCI Configuration (D22:F2)
Device ID And Vendor ID (IDE_HOST_DID_VID)
Status And Command (IDE_HOST_STS_CMD)
Class Code And Revision ID (IDE_HOST_CC_RID)
BIST, Header Type, Latency Timer, And Cache Line Size (IDE_HOST_BIST_HTYPE_LT_CLS)
IDE Primary Command Block IO BAR (IDE_HOST_PCMDIOBAR)
IDE Primary Control Block IO BAR (IDE_HOST_PCTLIOBAR)
IDE Secondary Command Block IO BAR (IDE_HOST_SCMDIOBAR)
IDE Secondary Control Block IO BAR (IDE_HOST_SCTLIOBAR)
IDE Bus Master Block IO BAR (IDE_HOST_BMIOBAR)
Subsystem ID And Subsystem Vendor ID (IDE_HOST_SID_SVID)
Capabilities List Pointer (IDE_HOST_CAPP)
Maximum Latency, Minimum Grant, Interrupt Pin And Interrupt Line (IDE_HOST_MAXL_MING_INTP_INTL)
MSI Message Control, Next Pointer And Capability ID (IDE_HOST_MSIMC_MSINP_MSICID)
MSI Message Address (IDE_HOST_MSIMA)
MSI Message Upper Address (IDE_HOST_MSIMUA)
MSI Message Data (IDE_HOST_MSIMD)
Power Management Capabilities, Next Pointer And Capability ID (IDE_HOST_PMCAP_PMNP_PMCID)
Power Management Data, Control/Status Register Bridge Support Extensions, Control And Status (IDE_HOST_PMD_PMCSRBSE_PMCSR)
Intel RST for PCIe Storage (Remapping) PCI Configuration (D24:F0)
AHCI Base Address (ABAR)
General Configuration Register (GCR)
General Status Register (GSR)
Configuration Access Index Register (CAIR)
Configuration Access Data Register (CADR)
Memory BAR Remap Configuration (MBRC)
I/O Remap Source Configuration (IOBRSC)
AHCI Index/Data Pair Capability Remap Configuration (AIDPCRC)
MSI-X Capability Remap Configuration (MXCRC)
MSI-X Table Remap Configuration (MXTRC)
MSI-X Table Base Address Register (MXTBAR)
MSI-X PBA Remap Configuration (MXPRC)
MSI-X PBA Base Address (MXPBAR)
NVM Remapping Device:Function (NRDF)
Extended General Configuration Register (EGCR)
Shadowed AHCI Ports Implemented (SAPI)
Remapping Host Device Function (RHDF)
Cycle Router Global Control (CRGC)
Fuse DW0 (FDW0)
Intel(R) Management Engine Interface PCI Configuration
Identifiers (HECI1_ID)
Command (HECI1_CMD)
Status (HECI1_STS)
Revision ID And Class Code (HECI1_RID_CC)
Cache Line Size (HECI1_CLS)
Master Latency Timer (HECI1_MLT)
Header Type (HECI1_HTYPE)
Built In Self-Test (HECI1_BIST)
MMIO Base Address Low (HECI1_MMIO_MBAR_LO)
MMIO Base Address High (HECI1_MMIO_MBAR_HI)
Sub System Identifiers (HECI1_SS)
Capabilities Pointer (HECI1_CAP)
Interrupt Information (HECI1_INTR)
Minimum Grant (HECI1_MGNT)
Maximum Latency (HECI1_MLAT)
Host Firmware Status Register 1 (HFSTS1)
Host Firmware Status Register 2 (HFSTS2)
Host General Status (HECI1_H_GS1)
PCI Power Management Capability ID (HECI1_PID)
PCI Power Management Capabilities (HECI1_PC)
PCI Power Management Control And Status (HECI1_PMCS)
Host Firmware Status Register 3 (HFSTS3)
Host Firmware Status Register 4 (HFSTS4)
Host Firmware Status Register 5 (HFSTS5)
Host Firmware Status Register 6 (HFSTS6)
Host General Status 2 (HECI1_H_GS2)
Host General Status 3 (HECI1_H_GS3)
Message Signaled Interrupt Identifiers (HECI1_MID)
Message Signaled Interrupt Message Control (HECI1_MC)
Message Signaled Interrupt Message Address (HECI1_MA)
Message Signaled Interrupt Upper Address (HECI1_MUA)
Message Signaled Interrupt Message Data (HECI1_MD)
Interrupt Delivery Mode (HECI1_HIDM)
Intel(R) Trace Hub Configuration
Vendor ID (VID)
Command (CMD)
Revision ID (RID)
Header Type (HT)
Trace Buffer Lower BAR (MTB_LBAR)
Trace Buffer Upper BAR (MTB_UBAR)
Software Lower BAR (SW_LBAR)
Software Upper BAR (SW_UBAR)
RTIT Lower BAR (RTIT_LBAR)
RTIT Upper BAR (RTIT_UBAR)
Subsystem Vendor ID (SVID)
Capabilities Pointer (CAP)
Interrupt Line (INTL)
MSI Capability ID (MSICID)
MSI Lower Message Address (MSILMA)
MSI Upper Message Address (MSIUMA)
MSI Message Data (MSIMD)
(FW_LBAR)
(FW_UBAR)
Device Specific Control (NPKDSC)
Power Control Enable Register (DEVIDLEPCE)
Interrupt
Master Initialization Command Word 1 (MICW1)
Master Initialization Command Word 2 (MICW2)
Master Initialization Command Word 3 (MICW3)
Master Initialization Command Word 4 (MICW4)
Master Operational Control Word 1 (MOCW1)
Master Operational Control Word 2 (MOCW2)
Master Operational Control Word 3 (MOCW3)
Slave Initialization Command Word 1 (SICW1)
Slave Initialization Command Word 2 (SICW2)
Slave Initialization Command Word 3 (SICW3)
Slave Initialization Command Word 4 (SICW4)
Slave Operational Control Word 1 (SOCW1)
Slave Operational Control Word 2 (SOCW2)
Slave Operational Control Word 3 (SOCW3)
Master Edge/Level Control (ELCR1)
Slave Edge/Level Control (ELCR2)
Interrupt PCR
PIRQA Routing Control (PARC)
PIRQB Routing Control (PBRC)
PIRQC Routing Control (PCRC)
PIRQD Routing Control (PDRC)
PIRQE Routing Control (PERC)
PIRQF Routing Control (PFRC)
PIRQG Routing Control (PGRC)
PIRQH Routing Control (PHRC)
PCI Interrupt Route 0 (PIR0)
PCI Interrupt Route 1 (PIR1)
PCI Interrupt Route 2 (PIR2)
PCI Interrupt Route 3 (PIR3)
PCI Interrupt Route 4 (PIR4)
PCI Interrupt Route 5 (PIR5)
General Interrupt Control (GIC)
Interrupt Polarity Control 0 (IPC0)
Interrupt Polarity Control 1 (IPC1)
Interrupt Polarity Control 2 (IPC2)
Interrupt Polarity Control 3 (IPC3)
ITSS Power Reduction Control (ITSSPRC)
NMI Control (NMI)
Master Message Control (MMC)
IO Trap
PSTH Control Register (PSTHCTL)
Trap Status Register (TRPSTS)
Trapped Cycle Register (TRPCYC1)
Trapped Write Data Register (TRPWRDATA1)
I/O Trap Registers 1 (IOTRP1_1)
I/O Trap Registers 1 (IOTRP1_2)
I/O Trap Registers 2 (IOTRP2_1)
I/O Trap Registers 2 (IOTRP2_2)
I/O Trap Registers 3 (IOTRP3_1)
I/O Trap Registers 3 (IOTRP3_2)
I/O Trap Registers 4 (IOTRP4_1)
I/O Trap Registers 4 (IOTRP4_2)
ISH
ISH Host Firmware Status (ISH_HOST_FWSTS)
Host Communication (HOST_COMM)
Inbound Doorbell Host To ISH (HOST2ISH_DOORBELL)
Outbound Doorbell ISH to Host (ISH2HOST_DOORBELL)
Outbound ISH to Host Message (ISH2HOST_MSG1)
Inbound Host to ISH Message (HOST2ISH_MSG1)
Remap 0 (REMAP0)
D0I3 Control (IPC_d0i3C_reg)
ISH PCH Configuration
Device ID and Vendor ID (DEVVENDID)
Status and Command (STATUSCOMMAND)
Revision ID and Class Code (REVCLASSCODE)
Cache Line Latency Header and BIST (CLLATHEADERBIST)
Base Address Register (BAR)
Base Address Register High (BAR_HIGH)
Base Address Register1 (BAR1)
Base Address Register1 High (BAR1_HIGH)
Subsystem Vendor and Subsystem ID (SUBSYSTEMID)
Capabilities Pointer (CAPABILITYPTR)
Interrupt Register (INTERRUPTREG)
PowerManagement Capability ID (POWERCAPID)
Power Management Control and Status (PMECTRLSTATUS)
Keyboard and Text (KT) PCI Configuration (D22:F3)
Device ID And Vendor ID (KT_HOST_DID_VID)
Status And Command (KT_HOST_STS_CMD)
Class Code And Revision ID (KT_HOST_CC_RID)
BIST, Header Type, Latency Timer, And Cache Line Size (KT_HOST_BIST_HTYPE_LT_CLS)
KT IO BAR (KT_HOST_IOBAR)
KT Memory BAR (KT_HOST_MEMBAR)
Cardbus CIS Pointer (KT_HOST_CCP)
Expansion ROM Base Address (KT_HOST_XRBAR)
Capabilities List Pointer (KT_HOST_CAPP)
Maximum Latency, Minimum Grant, Interrupt Pin And Interrupt Line (KT_HOST_MAXL_MING_INTP_INTL)
MSI Message Control, Next Pointer And Capability ID (KT_HOST_MSIMC_MSINP_MSICID)
MSI Message Address (KT_HOST_MSIMA)
MSI Message Upper Address (KT_HOST_MSIMUA)
MSI Message Data (KT_HOST_MSIMD)
Power Management Capabilities, Next Pointer And Capability ID (KT_HOST_PMCAP_PMNP_PMCID)
Power Management Data, Control/Status Register Bridge Support Extensions, Control And Status (KT_HOST_PMD_PMCSRBSE_PMCSR)
Subsystem ID And Subsystem Vendor ID (KT_HOST_SID_SVID)
LPC Configuration
Identifiers (IDTF)
Device Command (CMD)
Status (STS)
Revision ID (RID)
Class Code (CC)
Header Type (HTYPE)
Sub System Identifiers (SS)
Capability List Pointer (CAPP)
Serial IRQ Control (SCNT)
I/O Decode Ranges (IOD)
I/O Enables (IOE)
LPC Generic IO Range 1 (LGIR1)
LPC Generic IO Range 2 (LGIR2)
LPC Generic IO Range 3 (LGIR3)
LPC Generic IO Range 4 (LGIR4)
USB Legacy Keyboard/Mouse Control (ULKMC)
LPC Generic Memory Range (LGMR)
FWH ID Select 1 (FS1)
FWH ID Select 2 (FS2)
BIOS Decode Enable (BDE)
BIOS Control (BC)
PCI Clock Control (PCCTL)
OPI PCR
Virtual Channel 0 Resource Control (V0CTL)
Virtual Channel 0 Resource Status (V0STS)
Virtual Channel 1 Resource Control (V1CTL)
Virtual Channel 1 Resource Status (V1STS)
ME Virtual Channel (VCm) Resource Control (VMCTL)
ME Virtual Channel (VCm) Resource Status (VMSTS)
Uncorrectable Error Status (UES)
Uncorrectable Error Mask (UEM)
Uncorrectable Error Severity (UEV)
Correctable Error Status (CES)
Correctable Error Mask (CEM)
Root Error Command (REC)
Root Error Status (RES)
Error Source Identification (ESID)
DMI Control Register (DMIC)
IOSF Primary Control And Status (IPCS_IOSFSBCS)
DMI Port Link Control (DMILINKC)
DMI PLL Shutdown (DMIPLLDOWN)
DMI Power Management Control (DMIPMCTL)
Target Link Speed (TLS)
Link Configuration (LCFG)
LPC Generic I/O Range 1 (LPCLGIR1)
LPC Generic I/O Range 2 (LPCLGIR2)
LPC Generic I/O Range 3 (LPCLGIR3)
LPC Generic I/O Range 4 (LPCLGIR4)
LPC Generic Memory Range (LPCGMR)
LPC BIOS Decode Enable (LPCBDE)
General Control and Status (GCS)
I/O Trap Register 1 low (IOT1_LOW)
I/O Trap Register 1 high (IOT1_HIGH)
LPC I/O Decode Range (LPCIOD)
LPC I/O Enable (LPCIOE)
TCO Base Address (TCOBASE)
PM Base Address (PMBASEA)
PM Base Control (PMBASEC)
ACPI Base Address (ACPIBA)
ACPI Base Destination ID (ACPIBDID)
P2SB PCI Configuration
PCI Identifier (PCIID)
PCI Command (PCICMD)
Revision ID (PCIRID)
Class Code (PCICC)
PCI Header Type (PCIHTYPE)
Sideband Register Access BAR (SBREG_BAR)
Sideband Register BAR High DWORD (SBREG_BARH)
PCI Subsystem Identifiers (PCIHSS)
VLW Bus:Device:Function (VBDF)
ERROR Bus:Device:Function (EBDF)
Routing Configuration (RCFG)
High Performance Event Timer Configuration (HPTC)
IOxAPIC Configuration (IOAC)
IOxAPIC Bus:Device:Function (IBDF)
HPET Bus:Device:Function (HBDF)
Display Bus:Device:Function (DISPBDF)
ICC Register Offsets (ICCOS)
SBI Address (SBIADDR)
SBI Data (SBIDATA)
SBI Status (SBISTAT)
SBI Routing Identification (SBIRID)
SBI Extended Address (SBIEXTADDR)
P2SB Control (P2SBC)
Power Control Enable (PCE)
Sideband Register Posted 0 (SBREGPOSTED0)
Sideband Register Posted 1 (SBREGPOSTED1)
Sideband Register Posted 2 (SBREGPOSTED2)
Sideband Register Posted 3 (SBREGPOSTED3)
Sideband Register Posted 4 (SBREGPOSTED4)
Sideband Register Posted 5 (SBREGPOSTED5)
Sideband Register Posted 6 (SBREGPOSTED6)
Sideband Register Posted 7 (SBREGPOSTED7)
Endpoint Mask 0 (EPMASK0)
Endpoint Mask 1 (EPMASK1)
Endpoint Mask 2 (EPMASK2)
Endpoint Mask 3 (EPMASK3)
Endpoint Mask 4 (EPMASK4)
Endpoint Mask 5 (EPMASK5)
Endpoint Mask 6 (EPMASK6)
Endpoint Mask 7 (EPMASK7)
PCI Express* Port Configuration
Identifiers (ID)
Device Command; Primary Status (CMD_PSTS)
Revision ID;Class Code (RID_CC)
Cache Line Size; Primary Latency Timer; Header Type (CLS_PLT_HTYPE)
Bus Numbers; Secondary Latency Timer (BNUM_SLT)
I/O Base and Limit; Secondary Status (IOBL_SSTS)
Memory Base and Limit (MBL)
Prefetchable Memory Base and Limit (PMBL)
Prefetchable Memory Base Upper 32 Bits (PMBU32)
Prefetchable Memory Limit Upper 32 Bits (PMLU32)
Capabilities List Pointer (CAPP)
Interrupt Information; Bridge Control (INTR_BCTRL)
Capabilities List; PCI Express Capabilities (CLIST_XCAP)
Device Capabilities (DCAP)
Device Control; Device Status (DCTL_DSTS)
Link Capabilities (LCAP)
Link Control; Link Status (LCTL_LSTS)
Slot Capabilities (SLCAP)
Slot Control; Slot Status (SLCTL_SLSTS)
Root Control (RCTL)
Root Status (RSTS)
Device Capabilities 2 (DCAP2)
Device Control 2; Device Status 2 (DCTL2_DSTS2)
Link Capabilities 2 (LCAP2)
Link Control 2; Link Status 2 (LCTL2_LSTS2)
Message Signaled Interrupt Identifiers; Message Signaled Interrupt Message Control (MID_MC)
Message Signaled Interrupt Message Address (MA)
Message Signaled Interrupt Message Data (MD)
Subsystem Vendor Capability (SVCAP)
Subsystem Vendor IDs (SVID)
Power Management Capability; PCI Power Management Capabilities (PMCAP_PMC)
PCI Power Management Control And Status (PMCS)
Additional Configuration 1 (CCFG)
Miscellaneous Port Configuration 2 (MPC2)
Miscellaneous Port Configuration (MPC)
SMI / SCI Status (SMSCS)
Advanced Error Extended Reporting Capability Header (AECH)
Uncorrectable Error Status (UES)
Uncorrectable Error Mask (UEM)
Uncorrectable Error Severity (UEV)
Correctable Error Status (CES)
Correctable Error Mask (CEM)
Advanced Error Capabilities and Control (AECC)
Root Error Command (REC)
Root Error Status (RES)
Error Source Identification (ESID)
ACS Capability Register (ACSCAPR)
ACS Control Register (ACSCTLR)
L1 Sub-States Extended Capability Header (L1SECH)
L1 Sub-States Capabilities (L1SCAP)
L1 Sub-States Control 1 (L1SCTL1)
L1 Sub-States Control 2 (L1SCTL2)
Secondary PCI Express Extended Capability Header (SPEECH)
Link Control 3 (LCTL3)
Lane 0 and Lane 1 Equalization Control (L01EC)
Lane 2 and Lane 3 Equalization Control (L23EC)
PCI Express Replay Timer Policy 1 (PCIERTP1)
PCI Express Replay Timer Policy 2 (PCIERTP2)
PCI Express Configuration (PCIEDBG)
PCI Express Additional Link Control (PCIEALC)
Additional Configuration 2 (LTROVR)
Additional Configuration 3 (LTROVR2)
Thermal and Power Throttling (TNPT)
Additional Configuration 4 (PCIEPMECTL)
Equalization Configuration 1 (EQCFG1)
Remote Transmitter Preset/Coefficient List 1 (RTPCL1)
Remote Transmitter Preset/Coefficient List 2 (RTPCL2) (RTPCL2)
PMC I/O Based
Power Management 1 Enables and Status (PM1_EN_STS)
Power Management 1 Control (PM1_CNT)
Power Management 1 Timer (PM1_TMR)
SMI Control and Enable (SMI_EN)
SMI Status Register (SMI_STS)
General Purpose Event Control (GPE_CTRL)
Device Activity Status Register (DEVACT_STS)
PM2a Control Block (PM2A_CNT_BLK)
Over-Clocking WDT Control (OC_WDT_CTL)
General Purpose Event 0 Status [31:0] (GPE0_STS_31_0)
General Purpose Event 0 Status [63:32] (GPE0_STS_63_32)
General Purpose Event 0 Status [95:64] (GPE0_STS_95_64)
General Purpose Event 0 Status [127:96] (GPE0_STS[127:96])
General Purpose Event 0 Enable [31:0] (GPE0_EN_31_0)
General Purpose Event 0 Enable [63:32] (GPE0_EN_63_32)
General Purpose Event 0 Enable [95:64] (GPE0_EN_95_64)
General Purpose Event 0 Enable [127:96] (GPE0_EN[127:96])
PMC Memory Mapped
Last TSC Alarm Value[31:0] (TSC_ALARM_LO)
Last TSC Alarm Value[63:32] (TSC_ALARM_HI)
GPIO Configuration (GPIO_CFG)
Global Reset Causes (GBLRST_CAUSE0)
Global Reset Causes Register 1 (GBLRST_CAUSE1)
Host Partition Reset Causes (HPR_CAUSE0)
General PM Configuration A (GEN_PMCON_A)
General PM Configuration B (GEN_PMCON_B)
Configured Revision ID (CRID)
Extended Test Mode Register 3 (ETR3)
SET_STRAP_MSG_LOCK (SSML)
SET_STRAP_MSG_CONTROL (SSMC)
SET_STRAP_MSG_DATA (SSMD)
LATENCY_LIMIT_RESIDENCY_0 (LAT_LIM_RES_0)
LATENCY_LIMIT_RESIDENCY_1 (LAT_LIM_RES_1)
LATENCY_LIMIT_RESIDENCY_2 (LAT_LIM_RES_2)
SLP S0 RESIDENCY (SLP_S0_RES)
LATENCY LIMIT CONTROL (LLC)
Chipset Initialization Register 324 (CIR324)
Chipset Initialization Register B28 (CIRB28)
Configured Revision ID (CRID_UIP)
HSIO Power Management Configuration 1 (MODPHY_PM_CFG1)
HSIO Power Management Configuration 2 (MODPHY_PM_CFG2)
HSIO Power Management Configuration 3 (MODPHY_PM_CFG3)
HSIO Power Management Configuration 4 (MODPHY_PM_CFG4)
HSIO Power Management Configuration Reg 5 (MODPHY_PM_CFG5)
Chipset Initialization Register B40 (CIRB40)
Chipset Initialization Register B44 (CIRB44)
Chipset Initialization Register BA8 (CIRBA8)
Chipset Initialization Register BAC (CIRBAC)
Last PM_SYNC Message [31:0] (PM_SYNC_DATA_0)
Last PM_SYNC Message [63:32] (PM_SYNC_DATA_1)
CWB MDID Status Register (CWBMDIDSTATUS)
ACPI Control (ACTL)
PMC Throttling 1 (PMC_THROT_1)
Chipset Initialization Register 3E8 (CS_SD_CTL1)
Chipset Initialization Register 3EC (CS_SD_CTL2)
PGD Priority Agent Mapping Register 0 (PPAMR0)
PGD Priority Agent Mapping Register 1 (PPAMR1)
PGD Priority Agent Mapping Register 2 (PPAMR2)
PGD Priority Agent Mapping Register 3 (PPAMR3)
PGD Priority Agent Mapping Register 4 (PPAMR4)
PGD Priority Agent Mapping Register 5 (PPAMR5)
PGD Priority Agent Mapping Register 6 (PPAMR6)
PGD Priority Agent Mapping Register 7 (PPAMR7)
PGD Priority Agent Mapping Register 8 (PPAMR8)
PGD Priority Agent Mapping Register 9 (PPAMR9)
PGD Priority Agent Mapping Register 10 (PPAMR10)
PGD Priority Agent Mapping Register 11 (PPAMR11)
PGD Priority Agent Mapping Register 12 (PPAMR12)
PGD Priority Agent Mapping Register 13 (PPAMR13)
PGD Priority Agent Mapping Register 14 (PPAMR14)
PGD Priority Agent Mapping Register 15 (PPAMR15)
Chipset Initialization Register 580 (CIR580)
PGD PG_ACK Status Register 1 (PPASR1)
PFET Enable Ack Register 0 (PPFEAR0)
PFET Enable Ack Register 1 (PPFEAR1)
Chipset Initialization Register DA0 (CIRDA0)
PGD Misc Control Register (PMCR)
Host SW PG Control Register 1 (HSWPGCR1)
PGD PG_REQ Status Register 0 (PPRSR0)
PGD PG_REQ Status Register 1 (PPRSR1)
Static PG Function Disable 1 (ST_PG_FDIS1)
Static Function Disable Control 2 (ST_PG_FDIS2)
Non-Static PG Related Function Disable Register 1 (NST_PG_FDIS_1)
Always Running Timer Value 31:0 (ARTV_31_0)
Always Running Timer Value 31:0 (ARTV_63_32)
Timed GPIO Control 0 (TGPIOCTL0)
Timed GPIO 0 comparator Value 31:0 (TGPIOCOMPV0_31_0)
Timed GPIO comparator Value 63:32 (TGPIOCOMPV0_63_32)
Timed GPIO0 periodic Interval Value 31_0 (TGPIOPIV0_31_0)
Timed GPIO 0 periodic Interval Value 63_32 (TGPIOPIV0_63_32)
Timed GPIO Time Capture register 31_0 (TGPIOTCV0_31_0)
Timed GPIO0 Time Capture register 63_32 (TGPIOTCV0_63_32)
Timed GPIO0 Event Counter Capture register 31_0 (TGPIOECCV0_31_0)
Timed GPIO0 Event Counter Capture register 63_32 (TGPIOECCV0_63_32)
Timed GPIO0 Event Counter Register 31_0 (TGPIOEC0_31_0)
Timed GPIO0 Event Counter Register 63_32 (TGPIOEC0_63_32)
Timed GPIO Control 1 (TGPIOCTL1)
Timed GPIO 1 comparator Value 31:0 (TGPIOCOMPV1_31_0)
Timed GPIO comparator Value 63:32 (TGPIOCOMPV1_63_32)
Timed GPIO1 periodic Interval Value 31_0 (TGPIOPIV1_31_0)
Timed GPIO 1 periodic Interval Value 63_32 (TGPIOPIV1_63_32)
Timed GPIO Time Capture register 31_0 (TGPIOTCV1_31_0)
Timed GPIO Time Capture register 63_32 (TGPIOTCV1_63_32)
Timed GPIO0 Event Counter Capture register 31_0 (TGPIOECCV1_31_0)
Timed GPIO0 Event Counter Capture register 63_32 (TGPIOECCV1_63_32)
Timed GPIO1 Event Counter Register 31_0 (TGPIOEC1_31_0)
Timed GPIO Event Counter Register 63_32 (TGPIOEC1_63_32)
ART to RTC Ratio (ART_RTC_RATIO)
Wake Alarm Device Timer: AC (WADT_AC)
Wake Alarm Device Timer: DC (WADT_DC)
Wake Alarm Device Expired Timer: AC (WADT_EXP_AC)
Wake Alarm Device Expired Timer: DC (WADT_EXP_DC)
Power and Reset Status (PRSTS)
Power Management Configuration Reg 1 (PM_CFG)
PCH Power Management Status (PCH_PM_STS2)
S3 Power Gating Policies (S3_PWRGATE_POL)
S4 Power Gating Policies (S4_PWRGATE_POL)
S5 Power Gating Policies (S5_PWRGATE_POL)
DeepSx Configuration (DSX_CFG)
Power Management Configuration Reg 2 (PM_CFG2)
Chipset Initialization Register 48 (CIR48)
Chipset Initialization Register 4C (CIR4C)
Chipset Initialization Register 50 (CIR50)
Chipset Initialization Register 54 (CIR54)
Chipset Initialization Register 58 (CIR58)
Chipset Initialziation Register 68 (CIR68)
Chipset Initialization Register 80 (CIR80)
Chipset Initialization Register 84 (CIR84)
Chipset Initialization Register 88 (CIR88)
Chipset Initialization Register 8C (CIR8C)
Chipset Initialization Register 98 (CIR98)
Chipset Initizaliation Register A8 (CIRA8)
Chipset Initizaliation Register AC (CIRAC)
Chipset Initialization Register B0 (CIRB0)
Chipset Initialization Register B4 (CIRB4)
Chipset Initialization Register C0 (CIRC0)
PMSYNC Thermal Power Reporting Configuration (PMSYNC_TPR_CFG)
PM_SYNC Miscellaneous Configuration (PM_SYNC_MISC_CFG)
Chipset Initialization Register D0 (CIRD0)
Chipset Initialization Register D4 (CIRD4)
Power Management Configuration Reg 3 (PM_CFG3)
Chipset Initialization Register E4 (CIRE4)
Power Management Configuration Reg 4 (PM_CFG4)
CPU Early Power-on Configuration (CPU_EPOC)
ACPI Timer Control (ACPI_TMR_CTL)
Capability Disable Status 1 (N_STPG_FUSE_SS_DIS_RD_1)
Capability Disable Status 2 (STPG_FUSE_SS_DIS_RD_2)
SLP_S0# Debug 0 (SLP_S0_DBG_0)
SLP_S0# Debug 1 (SLP_S0_DBG_1)
SLP_S0# Debug 2 (SLP_S0_DBG_2)
VR Miscellaneous Control (VR_MISC_CTL)
PMC SSRAM PCI Configuration
Device Vendor ID (DEVVENDID)
Status and Command (STATUSCOMMAND)
Revision ID and Class Code (REVCLASSCODE)
Cache Line Latency Header and BIST (CLLATHEADERBIST)
32-bit Base Address Register (BAR)
BAR HIGH (BAR_HIGH)
32-bit Base Address Register1 (BAR1)
BAR1 HIGH (BAR1_HIGH)
Subsystem Identifiers (SUBSYSTEMID)
Capabilities Pointer (CAPABILITYPTR)
Interrupt Register (INTERRUPTREG)
Power Management Capability ID (POWERCAPID)
PME Control and Status (PMECTRLSTATUS)
PCI Device Capability Record (PCIDEVIDLE_CAP_RECORD)
D0I3_CONTROL_SW_LTR_MMIO_REG (D0I3_CONTROL_SW_LTR_MMIO_REG)
Device IDLE pointer register (DEVICE_IDLE_POINTER_REG)
Device PG Config (D0I3_MAX_POW_LAT_PG_CONFIG)
Power Management Configuration
Device Vendor ID (DEVVENDID)
Status and Command (STATUSCOMMAND)
Class Code and Revision ID (REVCLASSCODE)
Cache Line Latency Header and BIST (CLLATHEADERBIST)
PWRMBASE (BAR)
PWRMBASE HIGH (BAR_HIGH)
BAR 2 (BAR2)
Subsystem Identifiers (SUBSYSTEMID)
Capabilities Pointer (CAPABILITYPTR)
Interrupt Register (INTERRUPTREG)
Power Management Capability ID (POWERCAPID)
PME Control Status (PMECTRLSTATUS)
PCI Device Idle Capability Record (PCIDEVIDLE_CAP_RECORD)
SW LTR Update MMIO Location (D0I3_CONTROL_SW_LTR_MMIO_REG)
Device IDLE pointer register (DEVICE_IDLE_POINTER_REG)
D0I3_MAX_POW_LAT_PG_CONFIG (D0I3_MAX_POW_LAT_PG_CONFIG)
PSF1
D22:F0 PCI Configuration Space Enable (PSF_1_AGNT_T0_SHDW_PCIEN_CSE_RS0_D22_F0_OFFSET3)
D22:F1 PCI Configuration Space Enable (PSF_1_AGNT_T0_SHDW_PCIEN_CSE_RS0_D22_F1_OFFSET4)
D22:F2 PCI Configuration Space Enable (PSF_1_AGNT_T0_SHDW_PCIEN_PTIO_RS0_D22_F2_OFFSET5)
D22:F3 PCI Configuration Space Enable (PSF_1_AGNT_T0_SHDW_PCIEN_PTIO_RS0_D22_F3_OFFSET6)
D22:F4 PCI Configuration Space Enable (PSF_1_AGNT_T0_SHDW_PCIEN_CSE_RS0_D22_F4_OFFSET7)
D22:F5 PCI Configuration Space Enable (PSF_1_AGNT_T0_SHDW_PCIEN_CSE_RS0_D22_F5_OFFSET8)
D18:F0 PCI Configuration Space Enable (PSF_1_AGNT_T0_SHDW_PCIEN_KVMCC_RS3_D18_F0_OFFSET10)
D23:F0 PCI Configuration Space Enable (PSF_1_AGNT_T0_SHDW_PCIEN_VR_RS0_D23_F0_OFFSET31)
D28:F0 PCI Configuration Space Enable (PSF_1_AGNT_T1_SHDW_PCIEN_SPA_RS0_D28_F0_OFFSET32)
D28:F1 PCI Configuration Space Enable (PSF_1_AGNT_T1_SHDW_PCIEN_SPA_RS0_D28_F1_OFFSET33)
D28:F2 PCI Configuration Space Enable (PSF_1_AGNT_T1_SHDW_PCIEN_SPA_RS0_D28_F2_OFFSET34)
D28:F3 PCI Configuration Space Enable (PSF_1_AGNT_T1_SHDW_PCIEN_SPA_RS0_D28_F3_OFFSET35)
D28:F4 PCI Configuration Space Enable (PSF_1_AGNT_T1_SHDW_PCIEN_SPB_RS0_D28_F4_OFFSET36)
D28:F5 PCI Configuration Space Enable (PSF_1_AGNT_T1_SHDW_PCIEN_SPB_RS0_D28_F5_OFFSET37)
D28:F6 PCI Configuration Space Enable (PSF_1_AGNT_T1_SHDW_PCIEN_SPB_RS0_D28_F6_OFFSET38)
D28:F7 PCI Configuration Space Enable (PSF_1_AGNT_T1_SHDW_PCIEN_SPB_RS0_D28_F7_OFFSET39)
D29:F0 PCI Configuration Space Enable (PSF_1_AGNT_T1_SHDW_PCIEN_SPC_RS0_D29_F0_OFFSET40)
D29:F1 PCI Configuration Space Enable (PSF_1_AGNT_T1_SHDW_PCIEN_SPC_RS0_D29_F1_OFFSET41)
D29:F2 PCI Configuration Space Enable (PSF_1_AGNT_T1_SHDW_PCIEN_SPC_RS0_D29_F2_OFFSET42)
D29:F3 PCI Configuration Space Enable (PSF_1_AGNT_T1_SHDW_PCIEN_SPC_RS0_D29_F3_OFFSET43)
D29:F4 PCI Configuration Space Enable (PSF_1_AGNT_T1_SHDW_PCIEN_SPD_RS0_D29_F4_OFFSET44)
D29:F5 PCI Configuration Space Enable (PSF_1_AGNT_T1_SHDW_PCIEN_SPD_RS0_D29_F5_OFFSET45)
D29:F6 PCI Configuration Space Enable (PSF_1_AGNT_T1_SHDW_PCIEN_SPD_RS0_D29_F6_OFFSET46)
D29:F7 PCI Configuration Space Enable (PSF_1_AGNT_T1_SHDW_PCIEN_SPD_RS0_D29_F7_OFFSET47)
PSF Port 0 Configuration 0 (PSF_1_PSF_PORT_CONFIG_PG0_PORT0)
PSF Port 0 Configuration 1 (PSF_1_PSF_PORT_CONFIG_PG1_PORT0)
PSF Port 1 Configuration (PSF_1_PSF_PORT_CONFIG_PG1_PORT1)
PSF Port 2 Configuration (PSF_1_PSF_PORT_CONFIG_PG1_PORT2)
PSF Port 3 Configuration (PSF_1_PSF_PORT_CONFIG_PG1_PORT3)
PSF Port 4 Configuration (PSF_1_PSF_PORT_CONFIG_PG1_PORT4)
PSF Port 5 Configuration (PSF_1_PSF_PORT_CONFIG_PG1_PORT5)
PSF Port 6 Configuration (PSF_1_PSF_PORT_CONFIG_PG1_PORT6)
PSF Port 7 Configuration (PSF_1_PSF_PORT_CONFIG_PG1_PORT7)
PSF Port 8 Configuration (PSF_1_PSF_PORT_CONFIG_PG1_PORT8)
PSF Port 9 Configuration (PSF_1_PSF_PORT_CONFIG_PG1_PORT9)
Destination ID (PSF_1_PSF_MC_AGENT_MCAST0_RS0_TGT2_EOI)
PSF2
PSF Port 1 Configuration (PSF_2_PSF_PORT_CONFIG_PG1_PORT1)
PSF Port 2 Configuration (PSF_2_PSF_PORT_CONFIG_PG1_PORT2)
PSF Port 3 Configuration (PSF_2_PSF_PORT_CONFIG_PG1_PORT3)
PSF Port 4 Configuration (PSF_2_PSF_PORT_CONFIG_PG1_PORT4)
PSF Port 5 Configuration (PSF_2_PSF_PORT_CONFIG_PG1_PORT5)
D18:F0 PCI Configuration Space Enable (PSF_2_AGNT_T0_SHDW_PCIEN_TRH_RS0_D18_F0_OFFSET1)
D18:F5 PCI Configuration Space Enable (PSF_2_AGNT_T0_SHDW_PCIEN_UFSX2_RS0_D18_F5_OFFSET2)
D20:F0 PCI Configuration Space Enable (PSF_2_AGNT_T0_SHDW_PCIEN_XHCI_RS0_D20_F0_OFFSET3)
D20:F1 PCI Configuration Space Enable (PSF_2_AGNT_T0_SHDW_PCIEN_XDCI_RS0_D20_F1_OFFSET4)
D20:F4 PCI Configuration Space Enable (PSF_2_AGNT_T0_SHDW_PCIEN_NPK_RS0_D20_F4_OFFSET5)
D26:F0 PCI Configuration Space Enable (PSF_2_AGNT_T0_SHDW_PCIEN_EMMC_RS0_D26_F0_OFFSET6)
D31:F7 PCI Configuration Space Enable (PSF_2_AGNT_T0_SHDW_PCIEN_NPK_RS0_D31_F7_OFFSET7)
PSF Port 6 Configuration (PSF_2_PSF_PORT_CONFIG_PG1_PORT6)
PSF Port 7 Configuration (PSF_2_PSF_PORT_CONFIG_PG1_PORT7)
Rootspace Configuration (PSF_2_ROOTSPACE_CONFIG_RS0)
PSF Port 0 Configuration 0 (PSF_2_PSF_PORT_CONFIG_PG0_PORT0)
PSF Port 0 Configuration 1 (PSF_2_PSF_PORT_CONFIG_PG1_PORT0)
PSF3
D31:F0 PCI Configuration Space Enable (PSF_3_AGNT_T0_SHDW_PCIEN_SPI_RS0_D31_F0_OFFSET18)
D31:F1 PCI Configuration Space Enable (PSF_3_AGNT_T0_SHDW_PCIEN_P2S_RS0_D31_F1_OFFSET19)
Offset 1400h: PCI BAR (PSF_3_AGNT_T0_SHDW_BAR0_PMC_RS0_D31_F2_OFFSET20)
D31:F2 PCI Configuration Space Enable (PSF_3_AGNT_T0_SHDW_PCIEN_PMC_RS0_D31_F2_OFFSET20)
D31:F3 PCI Configuration Space Enable (PSF_3_AGNT_T0_SHDW_PCIEN_AUD_RS0_D31_F3_OFFSET21)
D31:F4 PCI Configuration Space Enable (PSF_3_AGNT_T0_SHDW_PCIEN_SMB_RS0_D31_F4_OFFSET22)
D31:F5 PCI Configuration Space Enable (PSF_3_AGNT_T0_SHDW_PCIEN_SPI_RS0_D31_F5_OFFSET23)
D18:F6 PCI Configuration Space Enable (PSF_3_AGNT_T0_SHDW_PCIEN_LPSS_RS0_D18_F6_OFFSET1)
D19:F0 PCI Configuration Space Enable (PSF_3_AGNT_T0_SHDW_PCIEN_ISH_RS0_D19_F0_OFFSET2)
D20:F2 PCI Configuration Space Enable (PSF_3_AGNT_T0_SHDW_PCIEN_PMC_RS0_D20_F2_OFFSET3)
D20:F3 PCI Configuration Space Enable (PSF_3_AGNT_T0_SHDW_PCIEN_CNVI_RS0_D20_F3_OFFSET4)
D20:F5 PCI Configuration Space Enable (PSF_3_AGNT_T0_SHDW_PCIEN_SDX_RS0_D20_F5_OFFSET5)
D21:F0 PCI Configuration Space Enable (PSF_3_AGNT_T0_SHDW_PCIEN_LPSS_RS0_D21_F0_OFFSET6)
D21:F1 PCI Configuration Space Enable (PSF_3_AGNT_T0_SHDW_PCIEN_LPSS_RS0_D21_F1_OFFSET7)
D31:F6 PCI Configuration Space Enable (PSF_3_AGNT_T0_SHDW_PCIEN_GBE_RS0_D31_F6_OFFSET24)
D19:F0 PCI Configuration Space Enable (PSF_3_AGNT_T0_SHDW_PCIEN_ISH_RS1_D19_F0_OFFSET25)
PSF Port 0 Configuration (PSF_3_PSF_PORT_CONFIG_PG0_PORT0)
PSF Port 0 Configuration (PSF_3_PSF_PORT_CONFIG_PG1_PORT0)
PSF Port 1 Configuration (PSF_3_PSF_PORT_CONFIG_PG1_PORT1)
PSF Port 2 Configuration (PSF_3_PSF_PORT_CONFIG_PG1_PORT2)
D21:F2 PCI Configuration Space Enable (PSF_3_AGNT_T0_SHDW_PCIEN_LPSS_RS0_D21_F2_OFFSET8)
D21:F3 PCI Configuration Space Enable (PSF_3_AGNT_T0_SHDW_PCIEN_LPSS_RS0_D21_F3_OFFSET9)
D25:F0 PCI Configuration Space Enable (PSF_3_AGNT_T0_SHDW_PCIEN_LPSS_RS0_D25_F0_OFFSET10)
D25:F1 PCI Configuration Space Enable (PSF_3_AGNT_T0_SHDW_PCIEN_LPSS_RS0_D25_F1_OFFSET11)
D25:F2 PCI Configuration Space Enable (PSF_3_AGNT_T0_SHDW_PCIEN_LPSS_RS0_D25_F2_OFFSET12)
D30:F0 PCI Configuration Space Enable (PSF_3_AGNT_T0_SHDW_PCIEN_LPSS_RS0_D30_F0_OFFSET13)
D30:F1 PCI Configuration Space Enable (PSF_3_AGNT_T0_SHDW_PCIEN_LPSS_RS0_D30_F1_OFFSET14)
PSF Port 3 Configuration (PSF_3_PSF_PORT_CONFIG_PG1_PORT3)
PSF Port 4 Configuration (PSF_3_PSF_PORT_CONFIG_PG1_PORT4)
PSF Port 5 Configuration (PSF_3_PSF_PORT_CONFIG_PG1_PORT5)
PSF Port 6 Configuration (PSF_3_PSF_PORT_CONFIG_PG1_PORT6)
PSF Port 7 Configuration (PSF_3_PSF_PORT_CONFIG_PG1_PORT7)
PSF Port 8 Configuration (PSF_3_PSF_PORT_CONFIG_PG1_PORT8)
PSF Port 9 Configuration (PSF_3_PSF_PORT_CONFIG_PG1_PORT9)
PSF Port 10 Configuration (PSF_3_PSF_PORT_CONFIG_PG1_PORT10)
PSF Port 11 Configuration (PSF_3_PSF_PORT_CONFIG_PG1_PORT11)
PSF Port 12 Configuration (PSF_3_PSF_PORT_CONFIG_PG1_PORT12)
D30:F2 PCI Configuration Space Enable (PSF_3_AGNT_T0_SHDW_PCIEN_LPSS_RS0_D30_F2_OFFSET15)
D30:F3 PCI Configuration Space Enable (PSF_3_AGNT_T0_SHDW_PCIEN_LPSS_RS0_D30_F3_OFFSET16)
PSF4
PSF Port 0 Configuration (PSF_4_PSF_PORT_CONFIG_PG0_PORT0)
PSF Port 0 Configuration (PSF_4_PSF_PORT_CONFIG_PG1_PORT0)
PSF Port 1 Configuration (PSF_4_PSF_PORT_CONFIG_PG1_PORT1)
PSF Port 2 Configuration (PSF_4_PSF_PORT_CONFIG_PG1_PORT2)
PSF Port 3 Configuration (PSF_4_PSF_PORT_CONFIG_PG1_PORT3)
PSF Port 4 Configuration (PSF_4_PSF_PORT_CONFIG_PG1_PORT4)
PSF5
PSF Port 0 Configuration (PSF_5_PSF_PORT_CONFIG_PG0_PORT0)
PSF Port 1 Configuration (PSF_5_PSF_PORT_CONFIG_PG0_PORT1)
PSF Port 2 Configuration (PSF_5_PSF_PORT_CONFIG_PG0_PORT2)
PSF Port 3 Configuration (PSF_5_PSF_PORT_CONFIG_PG0_PORT3)
PSF Port 4 Configuration (PSF_5_PSF_PORT_CONFIG_PG0_PORT4)
PSF Port 5 Configuration (PSF_5_PSF_PORT_CONFIG_PG0_PORT5)
PSF Port 6 Configuration (PSF_5_PSF_PORT_CONFIG_PG0_PORT6)
PSF Port Configuration (PSF_5_PSF_PORT_CONFIG_PG1_PORT0)
RTC Indexed
Seconds (Sec)
Seconds Alarm (Sec_Alarm)
Minutes (Minutes)
Minutes Alarm (Minutes_Alarm)
Hours (Hours)
Hours Alarm (Hours_Alarm)
Day of Week (Day_of_Week)
Day of Month (Day_of_Month)
Month (Month)
Year (Year)
Register A (RTC_REGA)
Register B - General Configuration (Register_B)
Register C - Flag Register (Register_C)
Register D - Flag Register (Register_D)
SATA ABAR
HBA Capabilities (GHC_CAP)
Global HBA Control (GHC)
Interrupt Status Register (IS)
Ports Implemented (GHC_PI)
AHCI Version (VS)
Enclosure Management Location (EM_LOC)
Enclosure Management Control (EM_CTL)
HBA Capabilities Extended (GHC_CAP2)
Vendor Specific (VSP)
Vendor-Specific Capabilities Register (VS_CAP)
RAID Platform ID (RPID)
Premium Feature Block (PFB)
SW Feature Mask (SFM)
Port 0 Command List Base Address (PxCLB0)
Port 0 Command List Base Address Upper 32-bits (PxCLBU0)
Port 0 FIS Base Address (PxFB0)
Port 0 FIS Base Address Upper 32-bits (PxFBU0)
Port 0 Interrupt Status (PxIS0)
Port 0 Interrupt Enable (PxIE0)
Port 0 Command (PxCMD0)
Port 0 Task File Data (PxTFD0)
Port 0 Signature (PxSIG0)
Port 0 Serial ATA Status (PxSSTS0)
Port 0 Serial ATA Status (PxSCTL0)
Port 0 Serial ATA Error (PxSERR0)
Port [0] Serial ATA Active (PxSACT0)
Port 0 Commands Issued (PxCI0)
Port 0 Device Sleep (PxDEVSLP0)
Port 1 Command List Base Address (PxCLB1)
Port 1 Command List Base Address Upper 32-bits (PxCLBU1)
Port 1 FIS Base Address (PxFB1)
Port 0 FIS Base Address Upper 32-bits (PxFBU1)
Port 1 Interrupt Status (PxIS1)
Port 0 Interrupt Enable (PxIE1)
Port 1 Command (PxCMD1)
Port 1 Task File Data (PxTFD1)
Port 1 Signature (PxSIG1)
Port 0 Serial ATA Status (PxSSTS1)
Port 1 Serial ATA Control (PxSCTL1)
Port 1 Serial ATA Error (PxSERR1)
Port 1 Serial ATA Active (PxSACT1)
Port 1 Commands Issued. (PxCI1)
Port 1 Device Sleep (PxDEVSLP1)
Port 2 Command List Base Address (PxCLB2)
Port 2 Command List Base Address Upper 32-bits (PxCLBU2)
Port 2 FIS Base Address (PxFB2)
Port 2 FIS Base Address Upper 32-bits (PxFBU2)
Port 2 Interrupt Status (PxIS2)
Port 2 Interrupt Enable (PxIE2)
Port 2 Command (PxCMD2)
Port 2 Task File Data (PxTFD2)
Port 2 Signature (PxSIG2)
Port 2 Serial ATA Status (PxSSTS2)
Port 2 Serial ATA Control (PxSCTL2)
Port 2 Serial ATA Error (PxSERR2)
Port 2 Serial ATA Active (PxSACT2)
Port 2 Commands Issued (PxCI2)
Port 2 Device Sleep (PxDEVSLP2)
SATA Configuration
Identifiers (ID)
Command (CMD)
Device Status (STS)
Revision ID (RID)
Programming Interface (PI)
Class Code (CC)
Cache Line Size (CLS)
Master Latency Timer (MLT)
Header Type (HTYPE)
MSI-X Table Base Address (MXTBA)
MSI-X Pending Bit Array Base Address (MXPBA)
AHCI Index Data Pair Base Address (AIDPBA)
AHCI Base Address (ABAR)
Sub System Identifiers (SS)
Capabilities Pointer (CAP)
Interrupt Information (INTR)
PCI Power Management Capability ID (PID)
PCI Power Management Capabilities (PC)
PCI Power Management Control and Status (PMCS)
Message Signalled Interrupt Identifier (MID)
Message Signalled Interrupt Message Control (MC)
Message Signalled Interrupt Message Address (MA)
Message Signalled Interrupt Message Data (MD)
Port Mapping Register (MAP)
Port Control and Status (PCS)
SATA General Configuration (SATAGC)
SATA Initialization Register Index (SIRI)
SATA Initialization Register Data (SIRD)
Serial ATA Capability Register 0 (SATACR0)
Serial ATA Capability Register 1 (SATACR1)
Scratch Pad (SP)
MSI-X Identifiers (MXID)
MSI-X Message Control (MXC)
MSI-X Table Offset / Table BIR (MXT)
MSI-X PBA Offset / PBA BIR (MXP)
BIST FIS Control/Status (BFCS)
BIST FIS Transmit Data 1 (BFTD1)
BIST FIS Transmit Data 2 (BFTD2)
SATA MXTBA
MSI-X Table Entries 0 Message Lower Address (MXTE0MLA)
MSI-X Table Entries 0 Message Upper Address (MXTE0MUA)
MSI-X Table Entries 0 Message Data (MXTE0MD)
MSI-X Table Entries 0 Vector Control (MXTE0VC)
MSI-X Table Entries 0 Message Lower Address (MXTE1MLA)
MSI-X Table Entries 0 Message Upper Address (MXTE1MUA)
MSI-X Table Entries 0 Message Data (MXTE1MD)
MSI-X Table Entries 0 Vector Control (MXTE1VC)
MSI-X Table Entries 0 Message Lower Address (MXTE2MLA)
MSI-X Table Entries 0 Message Upper Address (MXTE2MUA)
MSI-X Table Entries 0 Message Data (MXTE2MD)
MSI-X Table Entries 0 Vector Control (MXTE2VC)
MSI-X Table Entries 0 Message Lower Address (MXTE3MLA)
MSI-X Table Entries 0 Message Upper Address (MXTE3MUA)
MSI-X Table Entries 0 Message Data (MXTE3MD)
MSI-X Table Entries 0 Vector Control (MXTE3VC)
MSI-X Table Entries 0 Message Lower Address (MXTE4MLA)
MSI-X Table Entries 0 Message Upper Address (MXTE4MUA)
MSI-X Table Entries 0 Message Data (MXTE4MD)
MSI-X Table Entries 0 Vector Control (MXTE4VC)
MSI-X Table Entries 0 Message Lower Address (MXTE5MLA)
MSI-X Table Entries 0 Message Upper Address (MXTE5MUA)
MSI-X Table Entries 0 Message Data (MXTE5MD)
MSI-X Table Entries 0 Vector Control (MXTE5VC)
MSI-X Table Entries 0 Message Lower Address (MXTE6MLA)
MSI-X Table Entries 0 Message Upper Address (MXTE6MUA)
MSI-X Table Entries 0 Message Data (MXTE6MD)
MSI-X Table Entries 0 Vector Control (MXTE6VC)
MSI-X Table Entries 0 Message Lower Address (MXTE7MLA)
MSI-X Table Entries 0 Message Upper Address (MXTE7MUA)
MSI-X Table Entries 0 Message Data (MXTE7MD)
MSI-X Table Entries 0 Vector Control (MXTE7VC)
SDXC Additional Memory Mapped
Software LTR Value (SW_LTR_val)
Auto LTR Value (Auto_LTR_val)
Capabilities Bypass Control (Cap_byps)
Capabilities Bypass Register I (Cap_byps_reg1)
Capabilities Bypass Register II (Cap_byps_reg2)
Device Idle D0i3 (reg_D0i3)
Tx CMD Delay Control (Tx_CMD_dly)
Tx Delay Control 1 (Tx_DATA_dly_1)
Tx Delay Control 2 (Tx_DATA_dly_2)
Rx CMD Data Delay Control 1 (Rx_CMD_Data_dly_1)
Rx CMD Data Path Delay Control 2 (Rx_CMD_Data_dly_2)
Master DLL Software Control (Master_Dll)
Auto Tuning Value (Auto_tuning)
SDXC Memory Mapped
SDMA System Address (sdmasysaddr)
Block Size (blocksize)
Block Count (blockcount)
Argument1 (argument1)
Transfer Mode (transfermode)
Command (command)
Response [1-8] (response01)
Buffer Data Port (dataport)
Present State (presentstate)
Host Control 1 (hostcontrol1)
Power Control (powercontrol)
Block Gap Control (blockgapcontrol)
Wakeup Control (wakeupcontrol)
Clock Control (clockcontrol)
Timeout Control (timeoutcontrol)
Software Reset (softwarereset)
Normal Interrupt Status (normalintrsts)
Error Interrupt Status (errorintrsts)
Normal Interrupt Status Enable (normalintrstsena)
Error Interrupt Status Enable (errorintrstsena)
Normal Interrupt Signal Enable (normalintrsigena)
Error Interrupt Signal Enable (errorintrsigena)
Auto CMD12 Error Status (autocmderrsts)
Host Control 2 (hostcontrol2)
Capabilities (capabilities)
Maximum Current Capabilities (maxcurrentcap)
Force Event Register for AUTO CMD Error Status (ForceEventforAUTOCMDErrorStatus)
Force Event Register for Error Interrupt Status (forceeventforerrintsts)
ADMA Error Status (admaerrsts)
ADMA System Address Register 1 (admasysaddr01)
ADMA System Address Register 2 (admasysaddr2)
Preset Value Register for Initialization (presetvalue0)
Preset Value Register for Default Speed (presetvalue1)
Preset Value Register for High Speed (presetvalue2)
Preset Value Register for SDR12 (presetvalue3)
Preset Value Register for SDR25 (presetvalue4)
Preset Value Register for SDR50 (presetvalue5)
Preset Value Register for SDR104 (presetvalue6)
Preset Value Register for DDR50 (presetvalue7)
Slot Interrupt Status (slotintrsts)
SDXC PCI Configuration
Device ID and Vendor ID (DEVVENDID)
Status and Command (STATUSCOMMAND)
Rev ID & Class Code (REVCLASSCODE)
Cache Line & Latency & Header Type & BIST (CLLATHEADERBIST)
Base Address Low (BAR)
Base Address Register high (BAR_HIGH)
Base Address Register1 (BAR1)
(BAR1_HIGH)
Capabilities Pointer (CAPABILITYPTR)
Interrupt Line (INTERRUPTREG)
Power Management Capability ID Register (POWERCAPID)
Power Management Control and Status (PMECTRLSTATUS)
SW LTR update MMIO Location Register (D0I3_CONTROL_SW_LTR_MMIO_REG)
DOI3 Max Power & PG Config (D0I3_MAX_POW_LAT_PG_CONFIG)
General Purpose Read Write 1 (GEN_REGRW1)
General Purpose Read Write 2 (GEN_REGRW2)
General Purpose Read Write 3 (GEN_REGRW3)
General Purpose Read Write 4 (GEN_REGRW4)
General Purpose Input (GEN_INPUT_REG)
SMBus Configuration
Vendor ID (VID)
Device ID (DID)
Command (CMD)
Device Status (DS)
Revision ID (RID)
Programming Interface (PI)
Sub Class Code (SCC)
Base Class Code (BCC)
SMBus Memory Base Address_31_0 (SMBMBAR_31_0)
SMBus Memory Base Address_63_32 (SMBMBAR_63_32)
SMB Base Address (SBA)
Subsystem Vendor Identifiers (SVID)
Subsystem Identifiers (SID)
Interrupt Line (INTLN)
Interrupt Pin (INTPN)
Host Configuration (HCFG)
TCO Base Address (TCOBASE)
TCO Control (TCOCTL)
Host SMBus Timing (HTIM)
SMBus Power Gating (SMBSM)
SMBus I/O and Memory Mapped I/O
Host Status Register Address (HSTS)
Host Control Register (HCTL)
Host Command Register (HCMD)
Transmit Slave Address Register (TSA)
Data 0 Register (HD0)
Data 1 Register (HD1)
Host Block Data (HBD)
Packet Error Check Data Register (PEC)
Receive Slave Address Register (RSA)
Slave Data Register (SD)
Auxiliary Status (AUXS)
Auxiliary Control (AUXC)
SMLINK_PIN_CTL Register (SMLC)
SMBUS_PIN_CTL Register (SMBC)
Slave Status Register (SSTS)
Slave Command Register (SCMD)
Notify Device Address Register (NDA)
Notify Data Low Byte Register (NDLB)
Notify Data High Byte Register (NDHB)
SMBus TCO I/O
TCO_RLD Register (TRLD)
TCO_DAT_IN Register (TDI)
TCO_DAT_OUT Register (TDO)
TCO1_STS Register (TSTS1)
TCO2_STS Register (TSTS2)
TCO1_CNT Register (TCTL1)
TCO2_CNT Register (TCTL2)
TCO Message Registers (TMSG)
TCO_WDSTATUS Register (TWDS)
LEGACY_ELIM Register (LE)
TCO_TMR Register (TTMR)
SPI Configuration
Device ID and Vendor ID (BIOS_SPI_DID_VID)
Status and Command (BIOS_SPI_STS_CMD)
Revision ID and Class Code (BIOS_SPI_CC_RID)
BIST, Header Type, Latency Timer, Cache Line Size (BIOS_SPI_BIST_HTYPE_LT_CLS)
SPI BAR0 MMIO (BIOS_SPI_BAR0)
SPI Unsupported Request Status (BIOS_SPI_UR_STS_CTL)
BIOS Decode Enable (BIOS_SPI_BDE)
BIOS Control (BIOS_SPI_BC)
SPI Memory Mapped
BIOS Flash Primary Region (BIOS_BFPREG)
Hardware Sequencing Flash Status and Control (BIOS_HSFSTS_CTL)
Flash Address (BIOS_FADDR)
Discrete Lock Bits (BIOS_DLOCK)
Flash Data 0 (BIOS_FDATA0)
Flash Data 1 (BIOS_FDATA1)
Flash Data 2 (BIOS_FDATA2)
Flash Data 3 (BIOS_FDATA3)
Flash Data 4 (BIOS_FDATA4)
Flash Data 5 (BIOS_FDATA5)
Flash Data 6 (BIOS_FDATA6)
Flash Data 7 (BIOS_FDATA7)
Flash Data 8 (BIOS_FDATA8)
Flash Data 9 (BIOS_FDATA9)
Flash Data 10 (BIOS_FDATA10)
Flash Data 11 (BIOS_FDATA11)
Flash Data 12 (BIOS_FDATA12)
Flash Data 13 (BIOS_FDATA13)
Flash Data 14 (BIOS_FDATA14)
Flash Data 15 (BIOS_FDATA15)
Flash Region Access Permissions (BIOS_FRACC)
Flash Region 0 (BIOS_FREG0)
Flash Region 1 (BIOS_FREG1)
Flash Region 2 (BIOS_FREG2)
Flash Region 3 (BIOS_FREG3)
Flash Region 4 (BIOS_FREG4)
Flash Region 5 (BIOS_FREG5)
Flash Protected Range 0 (BIOS_FPR0)
Flash Protected Range 1 (BIOS_FPR1)
Flash Protected Range 2 (BIOS_FPR2)
Flash Protected Range 3 (BIOS_FPR3)
Flash Protected Range 4 (BIOS_FPR4)
Global Protected Range 0 (BIOS_GPR0)
Secondary Flash Region Access Permissions (BIOS_SFRACC)
Flash Descriptor Observability Control (BIOS_FDOC)
Flash Descriptor Observability Data (BIOS_FDOD)
Additional Flash Control (BIOS_AFC)
Vendor Specific Component Capabilities for Component 0 (BIOS_SFDP0_VSCC0)
Vendor Specific Component Capabilities for Component 1 (BIOS_SFDP1_VSCC1)
Parameter Table Index (BIOS_PTINX)
Parameter Table Data (BIOS_PTDATA)
SPI Bus Requester Status (BIOS_SBRS)
Thermal Reporting Configuration
Vendor Identification (VID)
Device Identification (DID)
Command (CMD)
Status (STS)
Revision Identification (RID)
Programming Interface (PI)
Sub Class Code (SCC)
Base Class Code (BCC)
Cache Line Size (CLS)
Latency Timer (LT)
Header Type (HTYPE)
Thermal Base (TBAR)
Thermal Base High DWord (TBARH)
Subsystem Vendor ID (SVID)
Subsystem ID (SID)
Capabilities Pointer (CAP_PTR)
Interrupt Line (INTLN)
Interrupt Pin (INTPN)
BIOS Assigned Thermal Base Address (TBARB)
BIOS Assigned Thermal Base High DWord (TBARBH)
Control Bits (CB)
PCI Power Management Capability ID (PID)
Power Management Capabilities (PC)
Power Management Control And Status (PCS)
Message Signaled Interrupt Identifiers (MID)
Message Signaled Interrupt Message Control (MC)
Message Signaled Interrupt Message Address (MA)
Message Signaled Interrupt Message Data (MD)
Thermal Reporting Memory Mapped
Temperature (TEMP)
Thermal Sensor Control (TSC)
Thermal Sensor Status (TSS)
Thermal Sensor Enable And Lock (TSEL)
Thermal Sensor Reporting Enable And Lock (TSREL)
Thermal Sensor SMI Control (TSMIC)
Catastrophic Trip Point (CTT)
Thermal Alert High Value (TAHV)
Thermal Alert Low Value (TALV)
Thermal Sensor Power Management (TSPM)
Throttle Levels (TL)
Throttle Level 2 (TL2)
PCH Hot Level (PHL)
PHL Control (PHLC)
Thermal Alert Status (TAS)
PCI Interrupt Event Enables (TSPIEN)
General Purpose Event Enables (TSGPEN)
Thernak Controller Function Disable (TCFD)
UART Additional Memory Mapped
CLOCKS (CLOCKS)
RESETS (RESETS)
Active LTR (ACTIVELTR_VALUE)
IDLE LTR (IDLELTR_VALUE)
reg_TX_BYTE_COUNT (TX_BYTE_COUNT)
reg_RX_BYTE_COUNT (RX_BYTE_COUNT)
SW SCRATCH 0 (SW_SCRATCH_0)
reg_CLOCK_GATE (CLOCK_GATE)
reg_REMAP_ADDR_LO (REMAP_ADDR_LO)
reg_REMAP_ADDR_HI (REMAP_ADDR_HI)
reg_DEVIDLE_CONTROL (DEVIDLE_CONTROL)
Capabilities (CAPABLITIES)
UART DMA Controller
DMA Transfer Source Address Low (SAR_LO0)
DMA Transfer Source Address High (SAR_HI0)
DMA Transfer Destination Address Low (DAR_LO0)
Source Status (SSTAT0)
Destination Status (DSTAT0)
DMA Transfer Destination Address High (DAR_HI0)
CH 0 Linked List Pointer Low (LLP_LO0)
CH0 Linked List Pointer High (LLP_HI0)
Source Status Address Low (SSTATAR_LO0)
Source Status Address High (SSTATAR_HI0)
Destination Status Address Low (DSTATAR_LO0)
Destination Status Address High (DSTATAR_HI0)
DMA Transfer Configuration Low (CFG_LO0)
DMA Transfer Configuration High (CFG_HI0)
Source Gather (SGR0)
Destination Scatter (DSR0)
CH 1 Linked List Pointer Low (LLP_LO1)
CH1 Linked List Pointer High (LLP_HI1)
Raw Interrupt Status (RawTfr)
Raw Status for Block Interrupts (RawBlock)
Raw Status for Source Transaction Interrupts (RawSrcTran)
Raw Status for Destination Transaction Interrupts (RawDstTran)
Raw Status for Error Interrupts (RawErr)
Interrupt Status (StatusTfr)
Status for Block Interrupts (StatusBlock)
Status for Source Transaction Interrupts (StatusSrcTran)
Status for Destination Transaction Interrupts (StatusDstTran)
Status for Error Interrupts (StatusErr)
Mask for Transfer Interrupts (MaskTfr)
Mask for Block Interrupts (MaskBlock)
Mask for Source Transaction Interrupts (MaskSrcTran)
Mask for Destination Transaction Interrupts (MaskDstTran)
Mask for Error Interrupts (MaskErr)
Clear for Transfer Interrupts (ClearTfr)
Clear for Block Interrupts (ClearBlock)
Clear for Source Transaction Interrupts (ClearSrcTran)
Clear for Destination Transaction Interrupts (ClearDstTran)
Clear for Error Interrupts (ClearErr)
Combined Status register (StatusInt)
DMA Configuration (DmaCfgReg)
DMA Channel Enable (ChEnReg)
Control Register Low (CTL_LO0)
Control Register High (CTL_HI0)
UART Memory Mapped
Receive Buffer Register (RBR)
Transmit Holding Register (THR)
Divisor Latch Low Register (DLL)
Interrupt Enable Register (IER)
Divisor Latch High (DLH)
Interrupt Identification (IIR)
FIFO Control (FCR)
Line Control Register (LCR)
MCR (MCR)
LSR (LSR)
MSR (MSR)
SCR (SCR)
SRBR_STHR0 (SRBR_STHR0)
FAR (FAR)
TFR (TFR)
RFW (RFW)
USR (USR)
TFL (TFL)
RFL (RFL)
SRR (SRR)
SRTS (SRTS)
SBCR (SBCR)
SDMAM (SDMAM)
SFE (SFE)
SRT (SRT)
STET (STET)
HTX (HTX)
DMASA (DMASA)
CPR (CPR)
UART PCI Configuration
Device ID and Vendor ID (DEVVENDID)
Status and Command (STATUSCOMMAND)
Revision ID and Class Code (REVCLASSCODE)
Cache Line Latency Header and BIST (CLLATHEADERBIST)
Base Address (BAR)
Base Address High (BAR_HIGH)
Base Address 1 (BAR1)
Base Address 1 High (BAR1_HIGH)
Subsystem Vendor and Subsystem ID (SUBSYSTEMID)
Capabilities Pointer (CAPABILITYPTR)
Interrupt Register (INTERRUPTREG)
Power Management Capability ID (POWERCAPID)
Power Management Control and Status (PMECTRLSTATUS)
PCI Device Idle Capability Record (PCIDEVIDLE_CAP_RECORD)
SW LTR update MMIO Location Register (D0I3_CONTROL_SW_LTR_MMIO_REG)
Device IDLE Pointer (DEVICE_IDLE_POINTER_REG)
Device PG Config (D0I3_MAX_POW_LAT_PG_CONFIG)
General Purpose Read Write 1 (GEN_REGRW1)
General Purpose Read Write 2 (GEN_REGRW2)
General Purpose Read Write 3 (GEN_REGRW3)
General Purpose Read Write 4 (GEN_REGRW4)
General Purpose Input (GEN_INPUT_REG)
xDCI MMIO Device
Device Configuration Register (DCFG)
Device Control Register (DCTL)
Device Event Enable Register (DEVTEN)
Device Status Register (DSTS)
Device Generic Command Parameter (DGCMDPAR)
Device Generic Command (DGCMD)
Device Active USB Endpoint Enable (DALEPENA)
Device Physical Endpoint-n Command Parameter 2 (DEPCMDPAR2)
Device Physical Endpoint-n Command Parameter 1 (DEPCMDPAR1)
Device Physical Endpoint-n Command Parameter 0 (DEPCMDPAR0)
Device Physical Endpoint-n Command (DEPCMD)
xDCI MMIO Global
Global SoC Bus Configuration 0 (GSBUSCFG0)
Global SoC Bus Configuration 1 (GSBUSCFG1)
Global Tx Threshold Control (GTXTHRCFG)
Global Rx Threshold Control (GRXTHRCFG)
Global Core Control (GCTL)
GPMSTS (GPMSTS)
Global Status (GSTS)
Bus Address Low (GBUSERRADDRLO)
Bus Address High (GBUSERRADDRHI)
GHWPARAMS0 (GHWPARAMS0)
GHWPARAMS1 (GHWPARAMS1)
GHWPARAMS2 (GHWPARAMS2)
GHWPARAMS3 (GHWPARAMS3)
GHWPARAMS4 (GHWPARAMS4)
GHWPARAMS5 (GHWPARAMS5)
GHWPARAMS6 (GHWPARAMS6)
GHWPARAMS7 (GHWPARAMS7)
GDBGFIFOSPACE (GDBGFIFOSPACE)
GDBGLTSSM (GDBGLTSSM)
GDBGLNMCC (GDBGLNMCC)
GDBGBMU (GDBGBMU)
GDBGLSP (GDBGLSP)
GDBGEPINFO0 (GDBGEPINFO0)
GDBGEPINFO1 (GDBGEPINFO1)
Global Transmit FIFO Size Register N (GTXFIFOSIZ0_0)
GRXFIFOSIZ0_0 (GRXFIFOSIZ0_0)
GEVNTADRLO_0 (GEVNTADRLO_0)
GEVNTADRHI_0 (GEVNTADRHI_0)
GEVNTCOUNT_0 (GEVNTCOUNT_0)
GTXFIFOPRIDEV (GTXFIFOPRIDEV)
xDCI PCI Configuration
Device ID and Vendor ID (DEVVENDID)
Status and Command (STATUSCOMMAND)
Base Address Register (BAR)
Base Address Register1 (BAR1)
Subsystem Vendor and Subsystem ID (SUBSYSTEMID)
Capabilities Pointer (CAPABILITYPTR)
Interrupt Register (INTERRUPTREG)
PowerManagement Capability ID (POWERCAPID)
Power Management Control and Status (PMECTRLSTATUS)
PCI Device Idle Capability Record (PCIDEVIDLE_CAP_RECORD)
Device ID and Vendor Specific Register (DEVID_VEND_SPECIFIC_REG)
SW LTR Update MMIO Location Register (D0I3_CONTROL_SW_LTR_MMIO_REG)
Device IDLE pointer register (DEVICE_IDLE_POINTER_REG)
(D0I3_MAX_POW_LAT_PG_CONFIG)
xHCI Configuration
Vendor ID (VID)
Device ID (DID)
Command (CMD)
Device Status (STS)
Revision ID (RID)
Programming Interface (PI)
Sub Class Code (SCC)
Base Class Code (BCC)
Master Latency Timer (MLT)
Header Type (HT)
Memory Base Address (MBAR)
USB Subsystem Vendor ID (SSVID)
USB Subsystem ID (SSID)
Capabilities Pointer (CAP_PTR)
Interrupt Line (ILINE)
Interrupt Pin (IPIN)
XHC System Bus Configuration 1 (XHCC1)
XHC System Bus Configuration 2 (XHCC2)
Clock Gating (XHCLKGTEN)
Audio Time Synchronization (AUDSYNC)
Serial Bus Release Number (SBRN)
Frame Length Adjustment (FLADJ)
Best Effort Service Latency (BESL)
PCI Power Management Capability ID (PM_CID)
Next Item Pointer #1 (PM_NEXT)
Power Management Capabilities (PM_CAP)
Power Management Control/Status (PM_CS)
Message Signaled Interrupt CID (MSI_CID)
Next item pointer (MSI_NEXT)
Message Signaled Interrupt Message Control (MSI_MCTL)
Message Signaled Interrupt Message Address (MSI_MAD)
Message Signaled Interrupt Upper Address (MSI_MUAD)
Message Signaled Interrupt Message Data (MSI_MD)
Power Control Enable (PCE_REG)
High Speed Configuration 2 (HSCFG2)
Super Speed Configuration 1 (SSCFG1)
XHCI USB3 Overcurrent Pin Mapping N (U3OCM)
XHCI USB2 Overcurrent Pin Mapping N (U2OCM)
xHCI Memory Mapped
Capability Registers Length (CAPLENGTH)
Host Controller Interface Version Number (HCIVERSION)
Structural Parameters 1 (HCSPARAMS1)
Structural Parameters 2 (HCSPARAMS2)
Structural Parameters 3 (HCSPARAMS3)
Capability Parameters (HCCPARAMS)
Doorbell Offset (DBOFF)
SuperSpeed Port Link Control (HOST_CTRL_PORT_LINK_REG)
USB2 Port Link Control 1 (USB2_LINK_MGR_CTRL_REG1)
USB2 Port Link Control 4 (USB2_LINK_MGR_CTRL_REG4)
Power Scheduler Control-0 (PWR_SCHED_CTRL0)
Power Scheduler Control-2 (PWR_SCHED_CTRL2)
AUX Power Management Control (AUX_CTRL_REG2)
USB2 PHY Power Management Control (USB2_PHY_PMC)
Runtime Register Space Offset (RTSOFF)
USB Command (USBCMD)
USB Status (USBSTS)
Page Size (PAGESIZE)
Device Notification Control (DNCTRL)
Command Ring Low (CRCR_LO)
Command Ring High (CRCR_HI)
xHCI Aux Clock Control Register (XHCI_AUX_CCR)
xHC Latency Tolerance Parameters - LTV Control (XLTP_LTV1)
xHC Latency Tolerance Parameters - High Idle Time Control (XLTP_HITC)
xHC Latency Tolerance Parameters - Medium Idle Time Control (XLTP_MITC)
xHC Latency Tolerance Parameters Low Idle Time Control (XLTP_LITC)
PDDIS_REG (PDDIS - xHCI Pull Down Disable Control)
LFPSONCOUNT_REG (LFPSONCOUNT_REG)
Device Context Base Address Array Pointer Low (DCBAAP_LO)
Device Context Base Address Array Pointer High (DCBAAP_HI)
Port N Status and Control USB2 (PORTSCN)
Port Power Management Status and Control USB2 (PORTPMSCN)
Port N Hardware LPM Control Register (PORTHLPMCN)
USB2 PM Control (USB2PMCTRL_REG)
USB Legacy Support Capability (USBLEGSUP)
USB Legacy Support Control Status (USBLEGCTLSTS)
Port Disable Override capability register (PDO_CAPABILITY)
USB2 Port Disable Override (USB2PDO)
USB3 Port Disable Override (USB3PDO)
Debug Capability ID Register (DCID)
Debug Capability Doorbell Register (DCDB)
Debug Capability Event Ring Segment Table Size Register (DCERSTSZ)
Debug Capability Event Ring Segment Table Base Address Register (DCERSTBA)
Debug Capability Event Ring Dequeue Pointer Register (DCERDP)
Debug Capability Control Register (DCCTRL)
Debug Capability Status Register (DCST)
Debug Capability Port Status and Control Register (DCPORTSC)
Debug Capability Context Pointer Register (DCCP)
Global Time Sync Capability (GLOBAL_TIME_SYNC_CAP_REG)
Port Status and Control USB2 (PORTSCXUSB3)
Port Power Management Status and Control USB2 (PORTPMSCX)
USB3 Port X Link Info (PORTLIX)
Microframe Index (RTMFINDEX)
Interrupter x Management (IMANx)
Interrupter x Moderation (IMODx)
Event Ring Segment Table Size x (ERSTSZx)
Event Ring Segment Table Base Address Low x (ERSTBA_LOx)
Event Ring Segment Table Base Address High x (ERSTBA_HIx)
Event Ring Dequeue Pointer Low x (ERDP_LOx)
Event Ring Dequeue Pointer High x (ERDP_HIx)
Door Bell x (DBx)
XECP_SUPP_USB2_0 (XECP_SUPP_USB2_0)
XECP_SUPP_USB2_1 (XECP_SUPP_USB2_1)
XECP_SUPP_USB2_2 (XECP_SUPP_USB2_2)
XECP_SUPP_USB3_3 (XECP_SUPP_USB2_3)
XECP_SUPP_USB2_4 (Full Speed) (XECP_SUPP_USB2_4)
XECP_SUPP_USB2_4 (Low Speed) (XECP_SUPP_USB2_5)
XECP_SUPP_USB2_5 (High Speed) (XECP_SUPP_USB2_6)
XECP_SUPP_USB3_0 (XECP_SUPP_USB3_0)
XECP_SUPP_USB3_1 (XECP_SUPP_USB3_1)
XECP_SUPP_USB3_2 (XECP_SUPP_USB3_2)
XECP_SUPP_USB3_3 (XECP_SUPP_USB3_3)
XECP_SUPP_USB3_4 (XECP_SUPP_USB3_4 Super Speed)
XECP_SUPP_USB3_5 (XECP_SUPP_USB3_5 Super Speed Plus)
XECP_SUPP_USB3_6 (XECP_SUPP_USB3_6)
XECP_SUPP_USB3_7 (XECP_SUPP_USB3_7)
XECP_SUPP_USB3_8 (XECP_SUPP_USB3_8)
XECP_SUPP_USB3_9 (XECP_SUPP_USB3_9)
Host Control Scheduler (HOST_CTRL_SCH_REG)
Power Management Control (PMCTRL_REG)
HOST_CTRL_MISC_REG (HOST_CTRL_MISC_REG)
HOST_CTRL_MISC_REG2 (HOST_CTRL_MISC_REG2)
SSPE_REG (SSPE_REG)
AUX Power Management Control (AUX_CTRL_REG1)
Global Time Sync Control (GLOBAL_TIME_SYNC_CTRL_REG)
Microframe Time (Local Time) (MICROFRAME_TIME_REG)
Always Running Time (ART) Low (ALWAYS_RUNNING_TIME_LOW)
Always Running Time (ART) High (ALWAYS_RUNNING_TIME_HIGH)
Dublin LFPS Register 4 (HOST_CTRL_SSP_LFPS_REG4)
Host Ctrl USB3 Soft Error Count Register 1 (HOST_CTRL_USB3_ERR_COUNT_REG1)
Maximum Latency, Minimum Grant, Interrupt Pin And Interrupt Line (IDE_HOST_MAXL_MING_INTP_INTL) – Offset 3c
This register contains the maximum latency, minumum grand, interrupt pin and interrupt level registers.
| Bit Range | Default | Access | Field Name and Description |
|---|---|---|---|
| 31:24 | 00h | RO | Maximum Latency (MAXL) Not implemented. Hardwired to 0. |
| 23:16 | 00h | RO | Minimum Grant (MING) Not implemented. Hardwired to 0. |
| 15:8 | 00h | RO/V | Interrupt Pin (INTP) This register specifies which interrupt pin IDE uses in PCI interrupt mode. |
| 7:0 | 00h | RW | Interrupt Line (INTL) The value written in this register indicates which input of thesystem interrupt controller, the device's interrupt pin is connected to. This value is used by theoperating system and the device driver, and has no affect on the hardware |