Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
USR (USR) – Offset 7c
UART Status Register
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
30:5 | - | - | Reserved
|
4 | 0h | RO | RFF (RFF) Receive FIFO Full. This is used to indicate that the receive FIFO is completely full. |
3 | 0h | RO | RFNE (RFNE) Receive FIFO Not Empty. This is used to indicate that the receive FIFO contains one or more entries. |
2 | 1h | RO | TFE (TFE) Transmit FIFO Empty. This is used to indicate that the transmit FIFO is completely empty. |
1 | 1h | RO | TFNF (TFNF) Transmit FIFO Not Full. This is used to indicate that the transmit FIFO in not full. |
0 | - | - | Reserved
|