Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
General Config Register (GEN_CFG) – Offset fed00010
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
62:2 | - | - | Reserved
|
1 | 0b | RW | Legacy Rout (LEG_RT_CNF) If the ENABLE_CNF bit and the LEG_RT_CNF bit are both set, the interrupts will be routed as follows: |
0 | 0b | RW | Overall Enable (ENABLE_CNF) This bit must be set to enable any of the timers to generateinterrupts. If this bit is 0, then the main counter will halt (will not increment) and no interrupts willbe caused by any of these timers. For level-triggered interrupts, if an interrupt is pending when theENABLE_CNF bit is changed from 1 to 0, the interrupt status indications (in the variousTxx_INT_STS bits) will not be cleared. Software must write to the Txx_INT_STS bits to clear the interrupts. |