Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
ID | Date | Version | Classification |
---|---|---|---|
615146 | 08/09/2019 | 1.2 | Public |
General Status Register (GSR) – Offset 304
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31 | 0b | RW | Port Configuration Check Disable (PCCD) When this bit is set to '1', internal port configuration check is disabled. When this bit is '0' (reset default), internal port configuration check is enabled. |
30 | 0b | RW/1C | Port Configuration Check Status (PCCS) This bit is set to '1' by hardware when internal port configuration check is enabled (GSR.PCCD='0') and a mismatch is detected. The bit is cleared to '0' by software writing a '1' to this bit position. |
29:21 | - | - | Reserved
|
20:1 | 0000Fh | RO | PCIe Lanes Remap Capable (PLRC) This field is bit significant, and it corresponds to PCIe Lane [20:1]. A '1' indicates the corresponding PCIe lane is remap capable with the option to select Cycle Router functionality on this lane. |
0 | - | - | Reserved
|