Global Reset Causes (GBLRST_CAUSE0) – Offset 1924 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

Intel® 400 Series Chipset On-Package Platform Controller Hub

Online Register Database

ID	Date	Version	Classification
615146	08/09/2019	1.2	Public

Global Reset Causes (GBLRST_CAUSE0) – Offset 1924

This register logs causes of host partition resets.

Bit Range	Default	Access	Field Name and Description
30:21	-	-	Reserved
20	0b	RW/1C/V	Over-Clocking WDT Expiration In ICC Survivability Mode (OC_WDT_EXP_ICCSURV) This bit is set to 1 by hardware when a global reset is triggered by the expiration of the over-clocking watchdog timer while running in a mode that has ICC survivability impact (OC_WDT_ICCSURV=1). This bit is reset by DSW_PWROK de-assertion.
19	0b	RW/1C/V	Over-Clocking WDT Expiration In Non-ICC Survivability Mode (OC_WDT_EXP_NO_ICCSURV) This bit is set to 1 by hardware when a global reset is triggered by the expiration of the over-clocking watchdog timer while running in a mode that does not have ICC survivability impact (OC_WDT_ICCSURV=0). This bit is reset by DSW_PWROK de-assertion.
18	-	-	Reserved
17	0b	RW/1C/V	Intel ME HW Uncorrectable Error (ME_UNCOR_ERR) This bit is set to '1' by hardware when a global reset is triggered by Intel ME hardware due to the detection of an uncorrectable ECC or parity error on a data read from one of its SRAMs. This bit is reset by DSW_PWROK de-assertion.
16	0b	RW/1C/V	CPU Thermal Runaway Watchdog Timer (CPU_THRM_WDT) This bit is set to '1' by hardware when a global reset is triggered by the expiration of the CPU Thermal Runaway Watchdog Timer.
15:13	-	-	Reserved
12	0b	RW/1C/V	SYS_PWROK Failure (SYSPWR_FLR) This bit is set to '1' by hardware when a global reset is triggered by an unexpected loss of SYS_PWROK. This bit is reset by DSW_PWROK de-assertion.
11	0b	RW/1C/V	PCH_PWROK Failure (PCHPWR_FLR) This bit is set to '1' by hardware when a global reset is triggered by an unexpected loss of PCH_PWROK. This bit is reset by DSW_PWROK de-assertion.
10	0b	RW/1C/V	PMC Firmware Global Reset (PMC_FW) This bit is set to '1' by hardware when a global reset is triggered by a request from PMC firmware (i.e. a write of '1' to the GBLRST_CTL.TRIG_GBL bit).
9	0b	RW/1C/V	Intel Management Engine Watchdog Timer (ME_WDT) This bit is set to '1' by hardware when a global reset is triggered by the second expiration of the Intel® Management Engine watchdog timer. This bit is reset by DSW_PWROK de-assertion.
8	0b	RW/1C/V	Power Management Controller Watchdog Timer (PMC_WDT) This bit is set to '1' by hardware when a global reset is triggered by the second expiration of the PMC watchdog timer. This bit is reset by DSW_PWROK de-assertion.
7	-	-	Reserved
6	0b	RW/1C/V	ME-Initiated Global Reset (ME_GBL) This bit is set to '1' by hardware when a global reset is triggered by Intel ME FW. This bit is reset by DSW_PWROK de-assertion.
5	0b	RW/1C/V	CPU Thermal Trip (CPU_TRIP) This bit is set to '1' by hardware when a global reset is triggered by a CPU thermal trip event (i.e. an assertion of the THRMTRIP# pin).
4	0b	RW/1C/V	ME-Initiated Power Button Override (ME_PBO) This bit is set to '1' by hardware when a global reset is triggered by ME-Initiated Power Button Override. This bit is reset by DSW_PWROK de-assertion.
3	0b	RW/1C/V	ICH Catastrophic Temperature Event (ICH_CAT_TMP) This bit is set to '1 by hardware when a global reset is triggered by a catastrophic temperature event from the ICH internal thermal sensor.
2	0b	RW/1C/V	PMC SUS RAM Uncorrectable Error (PMC_UNC_ERR) This bit is set to '1' by hardware when a global reset is triggered due to an uncorrectable parity error on a data read from one of the PMC SUS well register files. This bit is reset by DSW_PWROK de-assertion.
1	0b	RW/1C/V	Power Button Override (PB_OVR) This bit is set to '1' by hardware when a global reset is triggered by a power button override (i.e. an assertion of the PWRBTN# pin for 5 seconds). This bit is reset by DSW_PWROK de-assertion.
0	-	-	Reserved