Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
SMI Status (GPI_SMI_STS_GPP_C_0) – Offset 180
Register bits in this register are implemented for GPP_C signals that have SMI capability only. Other bits are reserved and RO.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
30:24 | - | - | Reserved
|
23 | 0b | RW/1C | GPI SMI Status (GPI_SMI_STS_GPPC_C_23) Same description as bit 22. |
22 | 0b | RW/1C | GPI SMI Status (GPI_SMI_STS_GPPC_C_22) This bit is set to 1 by hardware when a level event (See RxEdCfg,RxInv) is detected, and all the following conditions are true: |
21:0 | - | - | Reserved
|