Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
FIFO Control (FCR) – Offset 8
Note that the register can also be used as Interrupt Identification register (IIR)when it is read from.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
30:8 | - | - | Reserved
|
7:6 | 0h | WO | RCVR Trigger (RCVR) This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. The following trigger levels are supported: |
5:4 | 0h | WO | TX Empty Trigger (TET) This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: |
3 | - | - | Reserved
|
2 | 0h | WO | XMIT FIFO Reset (XFIFOR) This resets the control portion of the transmit FIFO and treats the FIFO as empty. |
1 | 0h | WO | RCVR FIFO Reset (RFIFOR) This resets the control portion of the receive FIFO and treats the FIFO as empty. |
0 | 1h | WO | FIFOs Enabled (FIFOE) This is used to indicate whether the FIFOs are enabled or disabled. |