Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
ID | Date | Version | Classification |
---|---|---|---|
615146 | 08/09/2019 | 1.2 | Public |
PCI Power Management Control Status & Data Register (PMCS_DR) – Offset cc
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
30:16 | - | - | Reserved
|
15 | 0x0 | RW/V | PME STATUS (PMES) This bit is set to 1 when the function detects a wake-up eventindependent of the state of the PMEE bit. Writing a 1 will clear this bit. |
14:13 | 0x0 | RW/V | DATA SCALE (DSC) This field indicates the scaling factor to be used when interpreting thevalue of the Data register. |
12:9 | 0x0 | RW | Data Select (DSL) This four-bit field is used to select which data is to be reported throughthe Data register (offset CFh) and Data_Scale field. These bits are writeable only when PowerManagement is enabled using NVM. |
8 | 0x0 | RW | PME Enable (PMEE) If Power Management is enabled in the NVM, writing a 1 to this bit willenable Wakeup. If Power Management is disabled in the NVM, writing a 1 to this bit has no affect,and will not set the bit to 1. This bit is not reset by Function Level Reset. |
7:2 | - | - | Reserved
|
1:0 | 0x0 | RW/V | Power State (PS) This field is used both to determine the current power state of the GbE LAN Controller and to set a new power state. The values are: |