I/O Trap Registers 4 (IOTRP4_2) – Offset 1e9c - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

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8254 Timer
Advanced Programmable Interrupt Controller (APIC)
APIC Indirect
CNVi PCI Configuration
DCI PCR
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EMMC Memory Mapped
EMMC PCI Configuration
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Enhanced SPI (eSPI) PCI Configuration
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GPIO Community 4
GSPI PCI Configuration
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IO Trap
ISH
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SDXC Additional Memory Mapped
SDXC Memory Mapped
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SPI Memory Mapped
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Thermal Reporting Memory Mapped
UART Additional Memory Mapped
UART DMA Controller
UART Memory Mapped
UART PCI Configuration
xDCI MMIO Device
xDCI MMIO Global
xDCI PCI Configuration
xHCI Configuration
xHCI Memory Mapped

I/O Trap Registers 4 (IOTRP4_2) – Offset 1e9c

These registers are used to specify the set of I/O cycles to be trapped and to enable this functionality.

Bit Range	Default	Access	Field Name and Description
30:18	-	-	Reserved
17	0b	RW	Read-Write Mask (TRP4RWM) When this bit is '1', the trapping logic will operate on both read and write cycles. When this bit is '0', the cycle must match the type specified in bit 48.
16	0b	RW	Read/Write (TRP4RW) 1 = Read, 0 = Write, the value in this field does not matter if bit 49 is set.
15:8	-	-	Reserved
7:4	0h	RW	Byte Enable Mask (TRP4BEM) A '1' in any bit position indicates that any value in the corresponding byte enable bit in a received cycle will be treated as a match. The corresponding bit in the Byte Enables field, below, is ignored.
3:0	0h	RW	Byte Enables (TRP4BE) Active-high, DWord-aligned byte enables

ISH

I/O Trap Registers 4 (IOTRP4_1) ISH