Discrete Lock Bits (BIOS_DLOCK) – Offset c - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

Intel® 400 Series Chipset On-Package Platform Controller Hub

Online Register Database

ID	Date	Version	Classification
615146	08/09/2019	1.2	Public

Discrete Lock Bits (BIOS_DLOCK) – Offset c

Lockable BIOS registers may be locked by either the global FLOCKDN bit or by the individual DLOCK bit. Each lockable bit in this register is locked either by itself or by the FLOCKDN bit.

Bit Range	Default	Access	Field Name and Description
30:17	-	-	Reserved
16	0b	RW/L	SSEQ Lock-Down (SSEQLOCKDN) BIOS Software Sequencing registers are locked when the logical OR of this bit and FLOCKDN is true. The affected registers are SSFSTS_CTL.SCF, PREOP_OPTYPE, OPMENU0, and OPMENU1. Once set to 1 this register is only cleared by host partition reset.
15	0b	RW/L	Spare1 (SPARE1) Once set to 1 this register is only cleared by host partition reset.
14	0b	RW/L	Spare2 (SPARE2) Once set to 1 this register is only cleared by host partition reset.
13	0b	RW/L	Spare3 (SPARE3) Once set to 1 this register is only cleared by host partition reset.
12	0b	RW/L	PR4 Lock-Down (PR4LOCKDN) BIOS PR4 register is locked when the logical OR of this bit and FLOCKDN is true. Once set to 1 this register is only cleared by BIOS partition reset.
11	0b	RW/L	PR3 Lock-Down (PR3LOCKDN) BIOS PR3 register is locked when the logical OR of this bit and FLOCKDN is true. Once set to 1 this register is only cleared by BIOS partition reset.
10	0b	RW/L	PR2 Lock-Down (PR2LOCKDN) BIOS PR2 register is locked when the logical OR of this bit and FLOCKDN is true. Once set to 1 this register is only cleared by BIOS partition reset.
9	0b	RW/L	PR1 Lock-Down (PR1LOCKDN) BIOS PR1 register is locked when the logical OR of this bit and FLOCKDN is true. Once set to 1 this register is only cleared by BIOS partition reset.
8	0b	RW/L	PR0 Lock-Down (PR0LOCKDN) BIOS PR0 register is locked when the logical OR of this bit and FLOCKDN is true. Once set to 1 this register is only cleared by BIOS partition reset.
7	0b	RW/L	Spare4 (SPARE4) Once set to 1 this register is only cleared by host partition reset.
6	0b	RW/L	Spare5 (SPARE5) Once set to 1 this register is only cleared by host partition reset.
5	0b	RW/L	Spare6 (SPARE6) Once set to 1 this register is only cleared by host partition reset.
4	0b	RW/L	Spare7 (SPARE7) Once set to 1 this register is only cleared by host partition reset.
3	0b	RW/L	SBMRAG Lock-Down (SBMRAGLOCKDN) BIOS SFRACC.BMRAG register bits are locked when the logical OR of this bit and FLOCKDN is true. Once set to 1 this register is only cleared by host partition reset.
2	0b	RW/L	SBMWAG Lock-Down (SBMWAGLOCKDN) BIOS SFRACC.BMWAG register bits are locked when the logical OR of this bit and FLOCKDN is true. Once set to 1 this register is only cleared by host partition reset.
1	0b	RW/L	BMRAG Lock-Down (BMRAGLOCKDN) BIOS FRACC.BMRAG register bits are locked when the logical OR of this bit and FLOCKDN is true. Once set to 1 this register is only cleared by host partition reset.
0	0b	RW/L	BMWAG Lock-Down (BMWAGLOCKDN) BIOS FRACC.BMWAG register bits are locked when the logical OR of this bit and FLOCKDN is true. Once set to 1 this register is only cleared by host partition reset.