Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
Capabilities List and Power Managment Capabilities Register (CLIST1_PMC) – Offset c8
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:27 | 0x0 | RW/V | PME_SUPPORT (PMES) This five-bit field indicates the power states in which the function mayassert PME#. It depend on PM Ena and AUX-PWR bits in word 0Ah in the NVM: |
26 | 0x0 | RW/V | D2_SUPPORT (D2S) The D2 state is not supported. |
25 | 0x0 | RW/V | D1_SUPPORT (D1S) The D1 state is not supported. |
24:22 | 0x0 | RW/V | AUX_CURRENT (AC) Required current defined in the Data register. |
21 | 0x1 | RW/V | Device Specific Initialization (DSI) Set to 1. The GbE LAN Controller requires its devicedriver to be executed following transition to the D0 un-initialized state. |
20 | - | - | Reserved
|
19 | 0x0 | RW/V | PME Clock (PMEC) Hardwired to 0. |
18:16 | 011b | RW/V | Version (VER) Hardwired to 010b to indicate support for Revision 1.1 of the PCI PowerManagement Specification. |
15:8 | 0xd0 | RW/V | Next Capability (NEXT) Value of D0h indicates the location of the next pointer. |
7:0 | 0x1 | RW/V | Capability ID (CID) Indicates the linked list item is a PCI Power Management Register. |