Power Management Configuration Reg 2 (PM_CFG2) – Offset 183c - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

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Power Management Configuration Reg 2 (PM_CFG2) – Offset 183c

Bit Range	Default	Access	Field Name and Description
31:29	000b	RW	Power Button Override Period (PBOP) This field determines, while the power button remains asserted, how long the PMC will wait before initiating a global reset. Encoding: 000b - 4 seconds 001b - 6 seconds 010b - 8 seconds 011b - 10 seconds 100b - 12 seconds 101b - 14 seconds Others - Reserved This bit is reset by DSW_PWROK de-assertion.
28	0b	RW/L	Power Button Native Mode Disable (PB_DIS) When this bit is '0' (default), the PMC's power button logic will act upon the input value from the GPIO unit, as normal. When this bit is set to '1', the PMC must force its internal version of the power button pin to '1'. This will result in the PMC logic constantly seeing the pin as de-asserted. This bit is reset by RTCRST# assertion.
27	-	-	Reserved
26	0b	RW/V	DRAM_RESET# Control (DRAM_RESET_CTL) BIOS uses this bit to control the DRAM_RESET# pin from the PCH, which is routed to the reset pin on the DRAM. Encoding: 0 = DRAM_RESET# output is asserted (driven low) 1 = DRAM_RESET# output is tri-stated. Note: This bit is cleared to '0' by HW when SLP_S4# goes low. This bit is reset by DSW_PWROK de-assertion.
25:0	-	-	Reserved

Chipset Initialization Register 48 (CIR48)

DeepSx Configuration (DSX_CFG) Chipset Initialization Register 48 (CIR48)