Hardware Sequencing Flash Status and Control (BIOS_HSFSTS_CTL) – Offset 4 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

Intel® 400 Series Chipset On-Package Platform Controller Hub

Online Register Database

ID	Date	Version	Classification
615146	08/09/2019	1.2	Public

Hardware Sequencing Flash Status and Control (BIOS_HSFSTS_CTL) – Offset 4

Bit Range	Default	Access	Field Name and Description
31	0b	RW	Flash SPI SMI# Enable (FSMIE) When set to 1, the SPI asserts an SMI# request whenever the Flash Cycle Done bit is 1.
30	-	-	Reserved
29:24	0h	RW	Flash Data Byte Count (FDBC) This field specifies the number of bytes to shift in or out during the data portion of the SPI cycle. The contents of this register are 0s based with 0b representing 1 byte and 3Fh representing 64 bytes. The number of bytes transferred is the value of this field plus 1. This field is ignored for the Block Erase command.
23:22	-	-	Reserved
21	0b	RW	Write Enable Type (WET) 0: Use 06h as the write enable instruction 1: Use 50h as the write enable instruction. Note that this setting is not supported as no supported flash devices require the 50h opcode to enable a non-volatile status register write.
20:17	0000b	RW	Flash Cycle (FCYCLE) This field defines the Flash SPI cycle type generated to the FLASH when the FGO bit is set as defined below: 0 Read (1 up to 64 bytes by setting FDBC) 1 Reserved 2 Write (1 up to 64 bytes by setting FDBC) 3 4k Block Erase 4 64k Sector erase 5 Read SFDP 6 Read JEDEC ID 7 write status 8 read status 9 RPMC Op1 A RPMC Op2 Flash controller hardware automatically inserts a write enable opcode prior to Write and erase operations. Hardware automatically polls for device not-busy using read status after write and erase operations. If the device does not support 64k erase size (or if it doesn't support SFDP) then only 4k is allowed. Note: if reserved 1 is programmed to this field, flash controller will handle it as if it is 0 (Read)
16	0b	RW/1S/V	Flash Cycle Go (FGO) A write to this register with a 1 in this bit initiates a request to the Flash SPI Arbiter to start a cycle. This register is cleared by hardware when the cycle is granted by the SPI arbiter to run the cycle on the SPI bus. When the cycle is complete, the FDONE bit is set. Software is forbidden to write to any register in the HSFLCTL register between the FGO bit getting set and the FDONE bit being cleared. Any attempt to violate this rule will be ignored by hardware. Hardware allows other bits in this register to be programmed for the same transaction when writing this bit to 1. This saves an additional memory write. This bit always returns 0 on reads.
15	0b	RW/L	Flash Configuration Lock-Down (FLOCKDN) When set to 1, those Flash Program Registers that are locked down by this FLOCKDN bit cannot be written. Once set to 1, this bit can only be cleared by a hardware reset.
14	0b	RO/V	Flash Descriptor Valid (FDV) This bit is set to a 1 if the Flash Controller read the correct Flash Descriptor Signature. If the Flash Descriptor Valid bit is not 1 , software cannot use the Hardware Sequencing registers, but must use the software sequencing registers. Any attempt to use the Hardware Sequencing registers will result in the FCERR bit being set
13	1b	RO/V	Flash Descriptor Override Pin-Strap Status (FDOPSS) This register reflects the value the Flash Descriptor Override Pin-Strap. '1': No override '0': The Flash Descriptor Override strap is set
12	0b	RW/L	PRR3 PRR4 Lock-Down (PRR34_LOCKDN) When set to 1, the BIOS PRR3 and PRR4 registers cannot be written. Once set to 1, this bit can only be cleared by a hardware reset.
11	0b	RW/L	Write Status Disable (WRSDIS) 0 = Write status operation may be issued using Hardware Sequencing. 1 = Write status is not allowed as a Hardware Sequencing operation. The flash controller will block the operation and set the FCERR bit when software sets the 'go' bit. This bit is locked when FLOCKDN is set.
10:9	-	-	Reserved
8	0b	RW/1C/V	SAF ctype error (H_SAF_CE) Hardware sets this bit to 1 when a transaction is returned from the eSPI controller with ctype error.
7	0b	RO/V	SAF Mode Active (H_SAF_MODE_ACTIVE) 0 : indicates flash is attached directly to the PCH via the SPI bus 1 : indicates flash is attached to the EC/BMC and is accessed via tunneled eSPI commands.
6	0b	RW/1C/V	SAF link Error (H_SAF_LE) Hardware sets this bit to 1 when a transaction is returned from the eSPI channel with link error.
5	0b	RO/V	SPI Cycle In Progress (H_SCIP) Hardware sets this bit when software sets the Flash Cycle Go (FGO) bit in the Hardware Sequencing Flash Control register. This bit remains set until the cycle completes on the SPI interface. Hardware automatically sets and clears this bit so that software can determine when read data is valid and/or when it is safe to begin programming the next command. Software must only program the next command when this bit is 0.
4	0b	RW/1C/V	SAF Data length Error (H_SAF_DLE) Hardware sets this bit to 1 when a transaction is returned from the eSPI channel with an incorrect data length.
3	0b	RW/1C/V	SAF Error (H_SAF_ERROR) Hardware sets this bit to 1 when a transaction is requested that is not supported by slave-attached flash, e.g. read status.
2	0b	RW/1C/V	Access Error Log (H_AEL) Hardware sets this bit to a 1 when an attempt was made to access the BIOS region using the direct access method or an access to the BIOS Program Registers that violated the security restrictions. This bit is simply a log of an access security violation. This bit is cleared by software writing a '1'.
1	0b	RW/1C/V	Flash Cycle Error (FCERR) Hardware sets this bit to 1 when a program register access is blocked to the FLASH due to one of the protection policies or when any of the programmed cycle registers is written while a programmed access is already in progress. This bit remains asserted until cleared by software writing a 1 or until hardware reset occurs. Software must clear this bit before setting the FLASH Cycle GO bit in this register.
0	0b	RW/1C/V	Flash Cycle Done (FDONE) The PCH sets this bit to 1 when the SPI Cycle completes after software previously set the FGO bit. This bit remains asserted until cleared by software writing a 1 or hardware reset. When this bit is set and the SPI SMI# Enable bit is set, an internal signal is asserted to the SMI# generation block. Software must make sure this bit is cleared prior to enabling the SPI SMI# assertion for a new programmed access.