Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
Stream Synchronization (SSYNC) – Offset 38
To synchronize two or more streams the corresponding SSYNC bits for the streams to be synchronized should be set to 1 before the 'RUN' bit for each stream is set.
The RUN bit for the corresponding stream must be set to 1 (and FIFORDY=1) prior to that stream's SSYNC bit being written to 0. To start multiple streams synchronously, the stream sync bits for those streams should be written to 0 at the same time. For all SSYNC bits on output engines that transition from 1 to 0 on the same write, the formatter will deliver a sample over the link in the same 48kHz frame. For all SSYNC bits on input engines that transition from 1 to 0 on the same write, the formatter will take stream data off the link and place it in the FIFO.
If synchronization is not desired, the stream synchronization bits may be left 0, and the stream will simply begin running normally when the stream's 'RUN' bit is set.
In addition to platform reset, FLR, and controller reset, the register is also reset by stream reset.
The number of SSYNC bits in this register is depending on the total number of stream DMA implemented.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
30:16 | - | - | Reserved
|
15:0 | 0h | RW | Stream Synchronization Bits (SSYNC) The Stream Synchronization bits, when set to 1, block data from being sent on or |