Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
Processing Pipe Control (PPCTL) – Offset 804
This register is not affected by stream reset.
Note that the PROCEN bit should only be modified when the corresponding host DMA and link DMA are idle, i.e. RUN bits are cleared, and the DMA contexts have been destroyed through SRST bits if it was previously activated.
Note that GPROCEN bit does not really enable or disable the Audio DSP operation, but mainly to workaround some legacy Intel HD Audio driver software such that if GPROCEN = 0, ADSPxBA (BAR2) is mapped to the Intel HD Audio memory mapped configuration registers, for compliancy with some legacy SW implementation. If GPROCEN = 1, only then ADSPxBA (BAR2) is mapped to the actual Audio DSP memory mapped configuration registers.
The number of PROCEN bits in this register is depending on the total number of stream DMA implemented.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31 | 0b | RW | Processing Interrupt Enable (PIE) Enables the general interrupt for the Audio DSP function. When set to 1 (and GIE is |
30:16 | - | - | Reserved
|
15:0 | 0h | RW | Processing Enable (PROCEN) When set to 1 the DMA engine associated with this stream will be enabled to route the audio |