Host Configuration (HCFG) – Offset 40 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

Introduction
8254 Timer
Advanced Programmable Interrupt Controller (APIC)
APIC Indirect
CNVi PCI Configuration
DCI PCR
- DCI Control (ECTRL)
EMMC Additional
EMMC Memory Mapped
EMMC PCI Configuration
eMMC PCR
- Dynamic Clock Gating Control (GPPRVRW1)
Enhanced SPI (eSPI) PCI Configuration
eSPI PCR
FIA Configuration PCR
GbE Configuration
GbE Memory Mapped I/O
Generic SPI (GSPI) Additional
Generic SPI (GSPI) DMA Controller
Generic SPI (GSPI) Memory Mapped
GPIO Community 0
GPIO Community 1
GPIO Community 2
GPIO Community 3
GPIO Community 4
GSPI PCI Configuration
High Definition Audio (D31:F3) Memory Mapped I/O
High Definition Audio (D31:F3) PCI Configuration
HPET Memory Mapped
I2C Additional
I2C DMA Controller
I2C Memory Mapped
I2C PCI Congifuration
IDE Redirect PCI Configuration (D22:F2)
Integrated Clock (ICC) Configuration
- CMU_ONE_DWORD25 (cmu_one_dword25)
Intel RST for PCIe Storage (Remapping) PCI Configuration (D24:F0)
Intel RST for PCIe Storage MMIO
Intel(R) Management Engine Interface PCI Configuration
Intel(R) MEI MMIO
- DEVIDLE Control (HECI1_DEVIDLEC)
Intel(R) Trace Hub Configuration
Intel® HD Audio PCR
- Function Configuration (FNCFG)
Interrupt
Interrupt PCR
IO Trap
ISH
ISH PCH Configuration
ISH PCR
- Power Management Control (PMCTL)
Keyboard and Text (KT) Additional Configuration
- Power Management Control and Status (KT_CSXE_PMD_PMCSRBSE_PMCSR)
Keyboard and Text (KT) PCI Configuration (D22:F3)
LPC Configuration
LPC PCR
- General Control And Function Disable (GCFD)
OPI PCR
P2SB PCI Configuration
PCI Express* Port Configuration
PMC I/O Based
PMC Memory Mapped
PMC SSRAM PCI Configuration
Power Management Configuration
Processor Interface Memory
PSF1
PSF2
PSF3
PSF4
PSF5
RTC Indexed
RTC PCR
SATA ABAR
SATA AIDP
- AHCI Index Register (INDEX)
- AHCI Data Register (DATA)
SATA Configuration
SATA Initialization (SIR) Index
SATA MXPBA
- MSI-X Pending Bit Array QW 0 (MXPQW0_DW0)
SATA MXTBA
SDXC (SD Card) PCR
- Dynamic Clock Gating Control (GPPRVRW1)
SDXC Additional Memory Mapped
SDXC Memory Mapped
SDXC PCI Configuration
SMBus Configuration
SMBus I/O and Memory Mapped I/O
SMBus PCR
SMBus TCO I/O
SPI Configuration
SPI Memory Mapped
Thermal Reporting Configuration
Thermal Reporting Memory Mapped
UART Additional Memory Mapped
UART DMA Controller
UART Memory Mapped
UART PCI Configuration
xDCI MMIO Device
xDCI MMIO Global
xDCI PCI Configuration
xHCI Configuration
xHCI Memory Mapped

Host Configuration (HCFG) – Offset 40

Host Configuration

Bit Range	Default	Access	Field Name and Description
6:5	-	-	Reserved
4	0b	RW/1L	SPD Write Disable (SPDWD) When this bit is set to 1, writes to SMBus addresses 50h – 57h are disabled.Note: This bit is R/WO and will be reset on PLTRST# assertion. This bit should be set by BIOS to‘1’. Software can only program this bit when both the START bitand Host Busy bit are ‘0’; otherwise, the write may result inundefined behavior.
3	0b	RW	SSRESET (SSRESET) Soft SMBUS Reset: When this bit is 1, the SMbus state machine and logic in PCH is reset. The HW will reset this bit to 0 when reset operation is completed.
2	0b	RW	I2C_EN (I2CEN) When this bit is 1, the Intel PCH is enabled to communicate with I2C devices. This will change the formatting of some commands. When this bit is 0, behavior is for SMBus.
1	0b	RW	SMB_SMI_EN (SSEN) When this bit is set, any source of an SMB interrupt will instead be routed to generate an SMI#.
0	0b	RW	HST_EN (HSTEN) When set, the SMB Host Controller interface is enabled to execute commands. The HST_INT_EN bit needs to be enabled in order for the SMB Host Controller to interrupt or SMI#. Additionally, the SMB Host Controller will not respond to any new requests until all interrupt requests have been cleared.

TCO Base Address (TCOBASE)

Interrupt Pin (INTPN) TCO Base Address (TCOBASE)