Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
Power Management Capabilities, Next Pointer And Capability ID (IDE_HOST_PMCAP_PMNP_PMCID) – Offset 50
This register contains the power management capabilities, next pointer And capability ID values.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:27 | 00000b | RO | PME Support (PMES) This 5-bit field indicates the power states in which |
26 | 0b | RO | D2 Support (D2S) Hardwired to 0 to indicate that this device does not support D2 |
25 | 0b | RO | D1 Support (D1S) Hardwired to 0 to indicate that this device does not support D1 |
24:22 | 000b | RO | Aux Current (AUXC) Not implemented. Hardwired to 0. |
21 | 1b | RO | Device Specific Initialization (DSI) indicates whether special initialization of this function is required |
20 | - | - | Reserved
|
19 | 0b | RO | PME Clock (PMECLK) Not implemented. Hardwired to 0. |
18:16 | 011b | RO | Version (VER) Hardwired to value of 011b indicates that this function complies with |
15:8 | 00h | RO | Next Item Pointer (NP) Indicates the pointer for the next entry in the capabilities list. |
7:0 | 01h | RO | Capability ID (CID) Hardwired to 01h to indicate the linked list item as the PCI Power Management registers |