Status And Command (IDE_HOST_STS_CMD) – Offset 4 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

Intel® 400 Series Chipset On-Package Platform Controller Hub

Online Register Database

ID	Date	Version	Classification
615146	08/09/2019	1.2	Public

Status And Command (IDE_HOST_STS_CMD) – Offset 4

This register contins the PCI status and command registers.

Bit Range	Default	Access	Field Name and Description
31	0b	RO	Detected Parity Error (DPE) Not implemented. Hardwired to 0.
30	0b	RO	Signaled System Error (SSE) Not implemented. Hardwired to 0.
29	0b	RW/1C/V	Received Master Abort (RMA) This bit must be set by a master device whenever its transaction (except for Special Cycle) is completed with Unsupported Request Completion Status (a.k.a. Master-Abort). All master devices must implement this bit.
28	0b	RW/1C/V	Received Target Abort (RTA) This bit must be set by a master device whenever its transaction is completed with Completer Abort Completion Status (a.k.a. Target-Abort). All master devices must implement this bit.
27	0b	RW/1C/V	Signaled Target Abort (STA) This bit must be set by a target device whenever it completes a Posted or Non-Posted transaction with a Completer Abort (a.k.a. Target-Abort) error. Devices that will never signal Completer Abort (a.k.a. Target-Abort) do not need to implement this bit.
26:25	00b	RO	Devsel Timing (DEVT) These bits encode the timing of DEVSEL#. There are three allowable timings for assertion of DEVSEL# as described below: 00b: fast; 01b: medium; 10b: slow; 11b: reserved. These bits are read-only and must indicate the slowest time that a device asserts DEVSEL# for any bus command except Configuration Read and Configuration Write. Hardwired to 00b.
24	0b	RO	Master Data Parity Error (MDPE) Not implemented. Hardwired to 0.
23	1b	RO	Fast Back To Back Capable (FBTBC) This bit indicates whether or not the target is capable of accepting fast back-to-back transactions when the transactions are not to the same agent. This bit can be set to 1 if the device can accept these transactions and must be set to 0 otherwise. Hardwired to 1.
22	-	-	Reserved
21	1b	RO	66 Mhz Capable (MCAP) This bit indicates whether or not this device is capable of running at 66 MHz. A value of 0 indicates 33 MHz. A value of 1 indicates that the device is 66 MHz capable. Hardwired to 1.
20	1b	RO	Capabilities List (CAPL) This optional read-only bit indicates whether or not this device implements the pointer for a New Capabilities linked list at offset 34h. A value of zero indicates that no New Capabilities linked list is available. A value of one indicates that the value read at offset 34h is a pointer in Configuration Space to a linked list of new capabilities.
19	0b	RO	Interrupt Status (INTS) This read-only bit reflects the state of the interrupt in the device/function. Only when the Interrupt Disable bit in the command register is a 0 and this Interrupt Status bit is a 1, will the device's/function's INTx# signal be asserted. Setting the Interrupt Disable bit to a 1 has no effect on the state of this bit. Read-only and hardwired to 0 for a device that does NOT support pin-based interrupt.
18:11	-	-	Reserved
10	0b	RW	Interrupt Disable (INTD) This bit disables the device/function from asserting INTx#. A value of 0 enables the assertion of its INTx# signal. A value of 1 disables the assertion of its INTx# signal. This bit's state after RST# is 0.
9	0b	RO	Fast Back To Back Enable (FBTBEN) Not implemented. Hardwired to 0.
8	0b	RO	System Error Enable (SERREN) Not implemented. Hardwired to 0.
7	-	-	Reserved
6	0b	RO	Parity Error Response (PERRR) Not implemented. Hardwired to 0.
5	0b	RO	VGA Palette Snoop (VGAPS) Not implemented. Hardwired to 0.
4	0b	RO	Memory Write And Invalidate Enable (MWRIEN) Not implemented. Hardwired to 0.
3	0b	RO	Special Cycles (SPCYC) Not implemented. Hardwired to 0.
2	0b	RW	Bus Master Enable (BME) This bit controls the PCI device's ability to act as a master for data transfers. This bit does not impact the generation of completions for split transactioncommands.
1	0b	RO	Memory Space Enable (MSE) Read-only and hardwired to 0 because IDE does NOT support Memory Space accesses.
0	0b	RW	IO Space Enable (IOSE) Controls a device's response to I/O Space accesses. A value of 0 disables the device response. A value of 1 allows the device to respond to I/O Space accesses. State after RST# is 0.