Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
Normal Interrupt Status (normalintrsts) – Offset 30
This register gives the status of all the interrupts
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
15 | 0h | RO | Error Interrupt (reg_errorintrsts) If any of the bits in the Error Interrupt Status Register are set, then this bit is set. Therefore the HD can test for an error by checking this bit first. |
14 | 0h | RW1C | Boot terminate Interrupt (normalintrsts_bootcomplete) This status is set if the boot operation get terminated |
13 | 0h | RW1C | Boot Acknowledge Rcv (normalintrsts_rcvbootack) This status is set if the boot acknowledge is receivedfrom device. |
12 | 0h | RO | Re-Tuning Event (normalintrsts_retuningevent) This status is set if Re-Tuning Request in the PresentState register changes from 0 to 1. Host Controller requests Host Driver to perform re-tuning for next data transfer. Current data transfer(not large block count) can be completed without retuning. |
11 | 0h | RO | INT_C_ Status (normalintrsts_intc) This status is set if INT_C is enabled and INT_C# pin isin low level. Writing this bit to 1 does not clear this bit. It is cleared by resetting the INT_C interrupt factor. |
10 | 0h | RO | INT_B_Status (normalintrsts_intb) This status is set if INT_B is enabled and INT_B# pin isin low level. Writing this bit to 1 does not clear this bit.It is cleared by resetting the INT_B interrupt factor. |
9 | 0h | RO | INT_A Status (normalintrsts_inta) This status is set if INT_A is enabled and INT_A# pin isin low level. Writing this bit to 1 does not clear this bit.It is cleared by resetting the INT_A interrupt factor. |
8 | 0h | RO | Card Interrupt (normalintrsts_cardintsts) In 1-bit mode, the HC shall detect the Card Interruptwithout SD Clock to support wakeup.In 4-bit mode, the card interrupt signal is sampledduring the interrupt cycle, so there are some sampledelays between the interrupt signal from the card andthe interrupt to the Host system. |
7 | 0h | RW1C | Card Removal (normalintrsts_cardremsts) This status is set if the Card Inserted in the PresentState register changes from 1 to 0.When the HD writes this bit to 1 to clear this status thestatus of the Card Inserted in the Present State registershould be confirmed. |
6 | 0h | RW1C | Card Insertion (normalintrsts_cardinssts) This status is set if the Card Inserted in the PresentState register changes from 0 to 1. |
5 | 0h | RW/1C | Buffer Read Ready (normalintrsts_bufrdready) This status is set if the Buffer Read Enable changes from 0 to 1. |
4 | 0h | RW1C | Buffer Write Ready (normalintrsts_bufwrready) This status is set if the Buffer Write Enable changesfrom 0 to 1. |
3 | 0h | RW1C | DMA Interrupt (normalintrsts_dmainterrupt) This status is set if the HC detects the Host DMA BufferBoundary in the Block Size Register. |
2 | 0h | RW1C | Block Gap Event (normalintrsts_blkgapevent) If the Stop At Block Gap Request in the Block GapControl Register is set, this bit is set. |
1 | 0h | RW1C | Transfer Complete (normalintrsts_xfercomplete) This bit is set when a read / write transaction iscompleted. |
0 | 0h | RW1C | Command Complete (normalintrsts_cmdcomplete) This bit is set when we get the end bit of the commandresponse (Except Auto CMD12 and Auto CMD23). |