Device Status and Command (ESPI_STS_CMD) – Offset 4 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

Intel® 400 Series Chipset On-Package Platform Controller Hub

Online Register Database

ID	Date	Version	Classification
615146	08/09/2019	1.2	Public

Device Status and Command (ESPI_STS_CMD) – Offset 4

Bit Range	Default	Access	Field Name and Description
31	0b	RW/1C/V	Detected Parity Error (DPE) Set when a parity error is detected on the internal bus. This bit gets set even if CMD.PERE is not set.
30	0b	RW/1C/V	Signaled System Error (SSE) Set when the eSPI controller signals a system error to the internal SERR# logic.
29	0b	RW/1C/V	Received Master Abort (RMA) Set when the bridge receives a completion with unsupported request status.
28	0b	RW/1C/V	Received Target Abort (RTA) Set when the bridge receives a completion with completer abort status.
27	0b	RW/1C/V	Signaled Target Abort (STA) Set when the bridge generates a completion packet with target abort status.
26:25	00b	RO	DEVSEL# Timing Status (DTS) Indicates medium timing, although this has no meaning on the HW.
24	0b	RW/1C/V	Data Parity Error Detected (DPD) Set when the bridge receives a completion packet from the backbone from a previous request, and detects a parity error, and CMD.PERE is set.
23	0b	RO	Fast Back to Back Capable (FBC) Reserved - bit has no meaning on the HW.
22	-	-	Reserved
21	0b	RO	66 MHz Capable (C66) Reserved - bit has no meaning on the HW.
20	0b	RO	Capabilities List (CLIST) Reserved.
19	0b	RO	Interrupt Status (INTS)
18:11	-	-	Reserved
10	1b	RO	Interrupt Disable (INTD)
9	0b	RO	Fast Back to Back Enable (FBE) Reserved as 0 per PCI-Express spec.
8	0b	RW	SERR# Enable (SEE) Enable SERR# to be generated if this bit is set.
7	0b	RO	Wait Cycle Control (WCC) Reserved as 0 per PCI-Express spec.
6	0b	RW	Parity Error Response Enable (PERE) This bit is set to 1 to enable response to parity errors when detected.
5	0b	RO	VGA Palette Snoop (VGA_PSE) Reserved as 0 per PCI-Express spec.
4	0b	RO	Memory Write and Invalidate Enable (MWIE) Reserved as 0 per PCI-Express spec.
3	0b	RO	Special Cycle Enable (SCE) Reserved as 0 per PCI-Express spec.
2	0b	RW	Bus Master Enable (BME) When this bit is set to 1, it enables the devices connected to eSPI to master upstream transactions to Host memory. Note: Any eSPI device connected to eSPI also has a BME bit in its Peripheral Channel Configuration register. This eSPI Slave BME bit also needs to be set in order for the Slave to send upstream memory requests. BIOS is responsible for setting both the eSPI-MC’s BME (this bit) and the eSPI Slaves’ BME bits using theTunneled Access to Slave Configuration mechanism. Furthermore, for proper operation, SW should ensure that the BME field in both the host and device are programmed with the same value (i.e. either 0 or 1)
1	1b	RO	Memory Space Enable (MSE) Memory space cannot be disabled.
0	1b	RO	I/O Space Enable (IOSE) I/O space cannot be disabled.